[S] Change in coreboot[master]: mb/google/brask/var/kuldax: Revise PsysPL2 to 150W for Pentium CPU

[Martin L Roth (Code Review)]

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68665 )

Change subject: mb/google/brask/var/kuldax: Revise PsysPL2 to 150W for Pentium CPU
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mb/google/brask/var/kuldax: Revise PsysPL2 to 150W for Pentium CPU

Pentium CPU will use 150W adaptor, this change revises PsysPL2 to 150W
based on fw_config.

BUG=b:253542746
TEST=Check CPU PsysPL2=150W in AP log with Pentium CPU.

Signed-off-by: David Wu 
Change-Id: I63b2a9d79454b20b60ba1317a8eebb3c10eff9d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68665
Tested-by: build bot (Jenkins) 
Reviewed-by: Nick Vaccaro 
---
M src/mainboard/google/brya/variants/kuldax/overridetree.cb
M src/mainboard/google/brya/variants/kuldax/ramstage.c
2 files changed, 43 insertions(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Nick Vaccaro: Looks good to me, approved

diff --git a/src/mainboard/google/brya/variants/kuldax/overridetree.cb b/src/mainboard/google/brya/variants/kuldax/overridetree.cb
index fdf37d5..a158788 100644
--- a/src/mainboard/google/brya/variants/kuldax/overridetree.cb
+++ b/src/mainboard/google/brya/variants/kuldax/overridetree.cb
@@ -3,6 +3,12 @@
    	option AUDIO_UNKNOWN	0
    	option NAU88L25B_I2S	1
    end
+	field BJ_POWER 3 4
+		option BJ_POWER_150W	0
+		option BJ_POWER_230W	1
+		option BJ_POWER_65W	2
+		option BJ_POWER_135W	3
+	end
 end

chip soc/intel/alderlake
diff --git a/src/mainboard/google/brya/variants/kuldax/ramstage.c b/src/mainboard/google/brya/variants/kuldax/ramstage.c
index 14a365a..4bec1d4 100644
--- a/src/mainboard/google/brya/variants/kuldax/ramstage.c
+++ b/src/mainboard/google/brya/variants/kuldax/ramstage.c
@@ -6,6 +6,7 @@
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
 #include <ec/google/chromeec/ec.h>
+#include <fw_config.h>
 #include <intelblocks/power_limit.h>

const struct cpu_power_limits limits[] = {
@@ -26,6 +27,15 @@
    { PCI_DID_INTEL_ADL_P_ID_3, 28, 150 },
 };

+const struct system_power_limits revise_sys_limits[] = {
+	/* SKU_ID, TDP (Watts), psys_pl2 (Watts) */
+	{ PCI_DID_INTEL_ADL_P_ID_10, 15, 150 },
+	{ PCI_DID_INTEL_ADL_P_ID_7, 15, 150 },
+	{ PCI_DID_INTEL_ADL_P_ID_6, 15, 150 },
+	{ PCI_DID_INTEL_ADL_P_ID_5, 28, 150 },
+	{ PCI_DID_INTEL_ADL_P_ID_3, 28, 150 },
+};
+
 /*
  * Psys_pmax considerations.
  *
@@ -55,6 +65,13 @@
 void variant_devtree_update(void)
 {
    size_t total_entries = ARRAY_SIZE(limits);
-	variant_update_psys_power_limits(limits, sys_limits, total_entries, &psys_config);
+
+	if (fw_config_probe(FW_CONFIG(BJ_POWER, BJ_POWER_65W)))
+		variant_update_psys_power_limits(limits, sys_limits, total_entries,
+							&psys_config);
+	else
+		variant_update_psys_power_limits(limits, revise_sys_limits,
+							total_entries, &psys_config);
+
    variant_update_power_limits(limits, total_entries);
 }