Change in coreboot[master]: soc/intel/common/cse: Add consistent HECI command id/group id naming
Hello Rizwan Qureshi,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/38247
to review the following change.
Change subject: soc/intel/common/cse: Add consistent HECI command id/group id naming ......................................................................
soc/intel/common/cse: Add consistent HECI command id/group id naming
Below changes are done: 1. Consistent HECI command/group ID naming. 2. Rename macros to match with Intel ME BIOS Spec. 3. Add description for structure members.
TEST=Build and Boot hatch board.
Change-Id: Ia902095483d5badf778d0c1faa6bf8cc431f0e50 Signed-off-by: Sridhar Siricilla sridhar.siricilla@intel.com Signed-off-by: Rizwan Qureshi rizwan.qureshi@intel.com --- M src/soc/intel/common/block/cse/cse.c 1 file changed, 22 insertions(+), 17 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/38247/1
diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 74a0020..6891ae0 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -67,24 +67,27 @@ #define MEI_HDR_CSE_ADDR_START 0 #define MEI_HDR_CSE_ADDR (((1 << 8) - 1) << MEI_HDR_CSE_ADDR_START)
-#define HECI_OP_MODE_SEC_OVERRIDE 5 +/* MKHI Command groups */ +#define MKHI_GROUP_ID_CBM 0x0 +#define MKHI_GROUP_ID_HMRFPO 0x5
/* Global Reset Command ID */ #define MKHI_GLOBAL_RESET_REQ 0xb -#define MKHI_GROUP_ID_CBM 0
/* RST Origin */ -#define GR_ORIGIN_BIOS_POST 2 - -#define MKHI_HMRFPO_GROUP_ID 5 +#define GR_ORIGIN_BIOS_POST 0x2
/* HMRFPO Command Ids */ -#define MKHI_HMRFPO_ENABLE 1 -#define MKHI_HMRFPO_GET_STATUS 3 +#define MKHI_HMRFPO_ENABLE 0x1 +#define MKHI_HMRFPO_GET_STATUS 0x3
-#define ME_HFS_CWS_NORMAL 5 -#define ME_HFS_MODE_NORMAL 0 -#define ME_HFS_TEMP_DISABLE 3 +/* ME Current Working States */ +#define ME_HFS1_CWS_NORMAL 0x5 + +/* ME Current Operation Modes */ +#define ME_HFS1_COM_NORMAL 0x0 +#define ME_HFS1_COM_SOFT_TEMP_DISABLE 0x3 +#define ME_HFS1_COM_SECOVER_MEI_MSG 0x5
static struct cse_device { uintptr_t sec_bar; @@ -258,14 +261,14 @@ }
/* - * Checks if CSE is in SEC_OVERRIDE operation mode. This is the mode where + * Checks if CSE is in ME_HFS1_COM_SECOVER_MEI_MSG operation mode. This is the mode where * CSE will allow reflashing of CSE region. */ static uint8_t check_cse_sec_override_mode(void) { union me_hfsts1 hfs1; hfs1.data = me_read_config32(PCI_ME_HFSTS1); - if (hfs1.fields.operation_mode == HECI_OP_MODE_SEC_OVERRIDE) + if (hfs1.fields.operation_mode == ME_HFS1_COM_SECOVER_MEI_MSG) return 1; return 0; } @@ -632,7 +635,7 @@ /* HMRFPO Enable message */ struct hmrfpo_enable_msg msg = { .hdr = { - .group_id = MKHI_HMRFPO_GROUP_ID, + .group_id = MKHI_GROUP_ID_HMRFPO, .command = MKHI_HMRFPO_ENABLE, }, .nonce = {0}, @@ -641,7 +644,9 @@ /* HMRFPO Enable response */ struct hmrfpo_enable_resp { struct mkhi_hdr hdr; + /* Base addr for factory data area, not relevant for client SKUs */ uint32_t fct_base; + /* Length of factory data area, not relevant for client SKUs */ uint32_t fct_limit; uint8_t status; uint8_t padding[3]; @@ -658,9 +663,9 @@ * - Working state is normal and * - Operation mode is normal or temporary disable mode. */ - if (hfs1.fields.working_state != ME_HFS_CWS_NORMAL || - (hfs1.fields.operation_mode != ME_HFS_MODE_NORMAL && - hfs1.fields.operation_mode != ME_HFS_TEMP_DISABLE)) { + if (hfs1.fields.working_state != ME_HFS1_CWS_NORMAL || + (hfs1.fields.operation_mode != ME_HFS1_COM_NORMAL && + hfs1.fields.operation_mode != ME_HFS1_COM_SOFT_TEMP_DISABLE)) { printk(BIOS_ERR, "HECI: ME not in required Mode\n"); goto failed; } @@ -697,7 +702,7 @@
struct hmrfpo_get_status_msg msg = { .hdr = { - .group_id = MKHI_HMRFPO_GROUP_ID, + .group_id = MKHI_GROUP_ID_HMRFPO, .command = MKHI_HMRFPO_GET_STATUS, }, };
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38247 )
Change subject: soc/intel/common/cse: Add consistent HECI command id/group id naming ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38247/1/src/soc/intel/common/block/... File src/soc/intel/common/block/cse/cse.c:
https://review.coreboot.org/c/coreboot/+/38247/1/src/soc/intel/common/block/... PS1, Line 70: /* MKHI Command groups */ : #define MKHI_GROUP_ID_CBM 0x0 : #define MKHI_GROUP_ID_HMRFPO 0x5 : : /* Global Reset Command ID */ : #define MKHI_GLOBAL_RESET_REQ 0xb : : /* RST Origin */ : #define GR_ORIGIN_BIOS_POST 0x2 : : /* HMRFPO Command Ids */ : #define MKHI_HMRFPO_ENABLE 0x1 : #define MKHI_HMRFPO_GET_STATUS 0x3 : : /* ME Current Working States */ : #define ME_HFS1_CWS_NORMAL 0x5 : : /* ME Current Operation Modes */ : #define ME_HFS1_COM_NORMAL 0x0 : #define ME_HFS1_COM_SOFT_TEMP_DISABLE 0x3 : #define ME_HFS1_COM_SECOVER_MEI_MSG 0x5 What do you think about moving the MKHI group id/command id related macros to cse.h. I think in one of the later patches, there is a new group id/command id added to another .c file. It would be better to put all these in one place.
Hello Patrick Rudolph, Subrata Banik, Rizwan Qureshi, build bot (Jenkins), Furquan Shaikh, Patrick Georgi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38247
to look at the new patch set (#2).
Change subject: soc/intel/common/cse: Add consistent HECI command id/group id naming ......................................................................
soc/intel/common/cse: Add consistent HECI command id/group id naming
Below changes are done: 1. Consistent HECI command/group ID naming. 2. Rename macros to match with Intel ME BIOS Spec. 3. Move command ids, group ids and related macros into cse.h 4. Add description for structure members.
TEST=Build and Boot hatch board.
Change-Id: Ia902095483d5badf778d0c1faa6bf8cc431f0e50 Signed-off-by: Sridhar Siricilla sridhar.siricilla@intel.com Signed-off-by: Rizwan Qureshi rizwan.qureshi@intel.com --- M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/include/intelblocks/cse.h 2 files changed, 31 insertions(+), 26 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/38247/2
Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38247 )
Change subject: soc/intel/common/cse: Add consistent HECI command id/group id naming ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38247/1/src/soc/intel/common/block/... File src/soc/intel/common/block/cse/cse.c:
https://review.coreboot.org/c/coreboot/+/38247/1/src/soc/intel/common/block/... PS1, Line 70: /* MKHI Command groups */ : #define MKHI_GROUP_ID_CBM 0x0 : #define MKHI_GROUP_ID_HMRFPO 0x5 : : /* Global Reset Command ID */ : #define MKHI_GLOBAL_RESET_REQ 0xb : : /* RST Origin */ : #define GR_ORIGIN_BIOS_POST 0x2 : : /* HMRFPO Command Ids */ : #define MKHI_HMRFPO_ENABLE 0x1 : #define MKHI_HMRFPO_GET_STATUS 0x3 : : /* ME Current Working States */ : #define ME_HFS1_CWS_NORMAL 0x5 : : /* ME Current Operation Modes */ : #define ME_HFS1_COM_NORMAL 0x0 : #define ME_HFS1_COM_SOFT_TEMP_DISABLE 0x3 : #define ME_HFS1_COM_SECOVER_MEI_MSG 0x5
What do you think about moving the MKHI group id/command id related macros to cse.h. […]
Agree. Moved the MKIH group ids, command id and related macros into cse.h
Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38247 )
Change subject: soc/intel/common/cse: Add consistent HECI command id/group id naming ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38247/1/src/soc/intel/common/block/... File src/soc/intel/common/block/cse/cse.c:
https://review.coreboot.org/c/coreboot/+/38247/1/src/soc/intel/common/block/... PS1, Line 70: /* MKHI Command groups */ : #define MKHI_GROUP_ID_CBM 0x0 : #define MKHI_GROUP_ID_HMRFPO 0x5 : : /* Global Reset Command ID */ : #define MKHI_GLOBAL_RESET_REQ 0xb : : /* RST Origin */ : #define GR_ORIGIN_BIOS_POST 0x2 : : /* HMRFPO Command Ids */ : #define MKHI_HMRFPO_ENABLE 0x1 : #define MKHI_HMRFPO_GET_STATUS 0x3 : : /* ME Current Working States */ : #define ME_HFS1_CWS_NORMAL 0x5 : : /* ME Current Operation Modes */ : #define ME_HFS1_COM_NORMAL 0x0 : #define ME_HFS1_COM_SOFT_TEMP_DISABLE 0x3 : #define ME_HFS1_COM_SECOVER_MEI_MSG 0x5
Agree. Moved the MKIH group ids, command id and related macros into cse. […]
Done
Hello Patrick Rudolph, Subrata Banik, Rizwan Qureshi, build bot (Jenkins), Furquan Shaikh, Patrick Georgi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38247
to look at the new patch set (#3).
Change subject: soc/intel/common/cse: Add consistent HECI command id/group id naming ......................................................................
soc/intel/common/cse: Add consistent HECI command id/group id naming
Below changes are done: 1. Consistent HECI command/group ID naming. 2. Rename macros to match with Intel ME BIOS Spec. 3. Move command ids, group ids and related macros into cse.h 4. Add description for structure members.
TEST=Build and Boot hatch board.
Change-Id: Ia902095483d5badf778d0c1faa6bf8cc431f0e50 Signed-off-by: Sridhar Siricilla sridhar.siricilla@intel.com Signed-off-by: Rizwan Qureshi rizwan.qureshi@intel.com --- M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/include/intelblocks/cse.h 2 files changed, 32 insertions(+), 27 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/38247/3
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38247 )
Change subject: soc/intel/common/cse: Add consistent HECI command id/group id naming ......................................................................
Patch Set 3: Code-Review+2
(2 comments)
https://review.coreboot.org/c/coreboot/+/38247/3/src/soc/intel/common/block/... File src/soc/intel/common/block/include/intelblocks/cse.h:
https://review.coreboot.org/c/coreboot/+/38247/3/src/soc/intel/common/block/... PS3, Line 164: /* Command GLOBAL_RESET_REQ Reset Types */ : #define GLOBAL_RESET 1 : #define HOST_RESET_ONLY 2 : #define CSE_RESET_ONLY 3 nit: This should probably be moved up under MKHI_CBM_GLOBAL_RESET_REQ on line 27.
https://review.coreboot.org/c/coreboot/+/38247/3/src/soc/intel/common/block/... PS3, Line 170: #define MKHI_HMRFPO_DISABLED 0 : #define MKHI_HMRFPO_LOCKED 1 : #define MKHI_HMRFPO_ENABLED 2 nit: This should probably be moved up under MKHI_HMRFPO_GET_STATUS on line 34.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38247 )
Change subject: soc/intel/common/cse: Add consistent HECI command id/group id naming ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38247/3/src/soc/intel/common/block/... File src/soc/intel/common/block/include/intelblocks/cse.h:
https://review.coreboot.org/c/coreboot/+/38247/3/src/soc/intel/common/block/... PS3, Line 23: nit: In the next CL, you are updating to use tabs for other macro definitions. It would be good to be consistent here as well.
Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38247 )
Change subject: soc/intel/common/cse: Add consistent HECI command id/group id naming ......................................................................
Patch Set 3:
(3 comments)
https://review.coreboot.org/c/coreboot/+/38247/3/src/soc/intel/common/block/... File src/soc/intel/common/block/include/intelblocks/cse.h:
https://review.coreboot.org/c/coreboot/+/38247/3/src/soc/intel/common/block/... PS3, Line 23:
nit: In the next CL, you are updating to use tabs for other macro definitions. […]
Addressed in the patch : https://review.coreboot.org/c/coreboot/+/38384/2
https://review.coreboot.org/c/coreboot/+/38247/3/src/soc/intel/common/block/... PS3, Line 167: #define CSE_RESET_ONLY 3 These flags grouped with cse_hmrfpo_enable() in the patch - https://review.coreboot.org/c/coreboot/+/38384/2.
https://review.coreboot.org/c/coreboot/+/38247/3/src/soc/intel/common/block/... PS3, Line 170: #define MKHI_HMRFPO_DISABLED 0 : #define MKHI_HMRFPO_LOCKED 1 : #define MKHI_HMRFPO_ENABLED 2
nit: This should probably be moved up under MKHI_HMRFPO_GET_STATUS on line 34.
These flags grouped with cse_hmrfpo_enable() in the patch - https://review.coreboot.org/c/coreboot/+/38384/2.
Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38247 )
Change subject: soc/intel/common/cse: Add consistent HECI command id/group id naming ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38247/3/src/soc/intel/common/block/... File src/soc/intel/common/block/include/intelblocks/cse.h:
https://review.coreboot.org/c/coreboot/+/38247/3/src/soc/intel/common/block/... PS3, Line 23:
Addressed in the patch : https://review.coreboot. […]
Done
Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38247 )
Change subject: soc/intel/common/cse: Add consistent HECI command id/group id naming ......................................................................
Patch Set 3:
(5 comments)
https://review.coreboot.org/c/coreboot/+/38247/1/src/soc/intel/common/block/... File src/soc/intel/common/block/cse/cse.c:
https://review.coreboot.org/c/coreboot/+/38247/1/src/soc/intel/common/block/... PS1, Line 70: /* MKHI Command groups */ : #define MKHI_GROUP_ID_CBM 0x0 : #define MKHI_GROUP_ID_HMRFPO 0x5 : : /* Global Reset Command ID */ : #define MKHI_GLOBAL_RESET_REQ 0xb : : /* RST Origin */ : #define GR_ORIGIN_BIOS_POST 0x2 : : /* HMRFPO Command Ids */ : #define MKHI_HMRFPO_ENABLE 0x1 : #define MKHI_HMRFPO_GET_STATUS 0x3 : : /* ME Current Working States */ : #define ME_HFS1_CWS_NORMAL 0x5 : : /* ME Current Operation Modes */ : #define ME_HFS1_COM_NORMAL 0x0 : #define ME_HFS1_COM_SOFT_TEMP_DISABLE 0x3 : #define ME_HFS1_COM_SECOVER_MEI_MSG 0x5
Done
Done
https://review.coreboot.org/c/coreboot/+/38247/3/src/soc/intel/common/block/... File src/soc/intel/common/block/include/intelblocks/cse.h:
https://review.coreboot.org/c/coreboot/+/38247/3/src/soc/intel/common/block/... PS3, Line 23:
Done
Done
https://review.coreboot.org/c/coreboot/+/38247/3/src/soc/intel/common/block/... PS3, Line 164: /* Command GLOBAL_RESET_REQ Reset Types */ : #define GLOBAL_RESET 1 : #define HOST_RESET_ONLY 2 : #define CSE_RESET_ONLY 3
nit: This should probably be moved up under MKHI_CBM_GLOBAL_RESET_REQ on line 27.
Done
https://review.coreboot.org/c/coreboot/+/38247/3/src/soc/intel/common/block/... PS3, Line 167: #define CSE_RESET_ONLY 3
These flags grouped with cse_hmrfpo_enable() in the patch - https://review.coreboot. […]
Done
https://review.coreboot.org/c/coreboot/+/38247/3/src/soc/intel/common/block/... PS3, Line 170: #define MKHI_HMRFPO_DISABLED 0 : #define MKHI_HMRFPO_LOCKED 1 : #define MKHI_HMRFPO_ENABLED 2
These flags grouped with cse_hmrfpo_enable() in the patch - https://review.coreboot. […]
Done
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38247 )
Change subject: soc/intel/common/cse: Add consistent HECI command id/group id naming ......................................................................
soc/intel/common/cse: Add consistent HECI command id/group id naming
Below changes are done: 1. Consistent HECI command/group ID naming. 2. Rename macros to match with Intel ME BIOS Spec. 3. Move command ids, group ids and related macros into cse.h 4. Add description for structure members.
TEST=Build and Boot hatch board.
Change-Id: Ia902095483d5badf778d0c1faa6bf8cc431f0e50 Signed-off-by: Sridhar Siricilla sridhar.siricilla@intel.com Signed-off-by: Rizwan Qureshi rizwan.qureshi@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/38247 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Furquan Shaikh furquan@google.com --- M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/include/intelblocks/cse.h 2 files changed, 32 insertions(+), 27 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved
diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 74a0020..0f50cc1 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -67,25 +67,6 @@ #define MEI_HDR_CSE_ADDR_START 0 #define MEI_HDR_CSE_ADDR (((1 << 8) - 1) << MEI_HDR_CSE_ADDR_START)
-#define HECI_OP_MODE_SEC_OVERRIDE 5 - -/* Global Reset Command ID */ -#define MKHI_GLOBAL_RESET_REQ 0xb -#define MKHI_GROUP_ID_CBM 0 - -/* RST Origin */ -#define GR_ORIGIN_BIOS_POST 2 - -#define MKHI_HMRFPO_GROUP_ID 5 - -/* HMRFPO Command Ids */ -#define MKHI_HMRFPO_ENABLE 1 -#define MKHI_HMRFPO_GET_STATUS 3 - -#define ME_HFS_CWS_NORMAL 5 -#define ME_HFS_MODE_NORMAL 0 -#define ME_HFS_TEMP_DISABLE 3 - static struct cse_device { uintptr_t sec_bar; } cse; @@ -258,14 +239,14 @@ }
/* - * Checks if CSE is in SEC_OVERRIDE operation mode. This is the mode where + * Checks if CSE is in ME_HFS1_COM_SECOVER_MEI_MSG operation mode. This is the mode where * CSE will allow reflashing of CSE region. */ static uint8_t check_cse_sec_override_mode(void) { union me_hfsts1 hfs1; hfs1.data = me_read_config32(PCI_ME_HFSTS1); - if (hfs1.fields.operation_mode == HECI_OP_MODE_SEC_OVERRIDE) + if (hfs1.fields.operation_mode == ME_HFS1_COM_SECOVER_MEI_MSG) return 1; return 0; } @@ -591,7 +572,7 @@ struct reset_message msg = { .hdr = { .group_id = MKHI_GROUP_ID_CBM, - .command = MKHI_GLOBAL_RESET_REQ, + .command = MKHI_CBM_GLOBAL_RESET_REQ, }, .req_origin = GR_ORIGIN_BIOS_POST, .reset_type = rst_type @@ -632,7 +613,7 @@ /* HMRFPO Enable message */ struct hmrfpo_enable_msg msg = { .hdr = { - .group_id = MKHI_HMRFPO_GROUP_ID, + .group_id = MKHI_GROUP_ID_HMRFPO, .command = MKHI_HMRFPO_ENABLE, }, .nonce = {0}, @@ -641,7 +622,9 @@ /* HMRFPO Enable response */ struct hmrfpo_enable_resp { struct mkhi_hdr hdr; + /* Base addr for factory data area, not relevant for client SKUs */ uint32_t fct_base; + /* Length of factory data area, not relevant for client SKUs */ uint32_t fct_limit; uint8_t status; uint8_t padding[3]; @@ -658,9 +641,9 @@ * - Working state is normal and * - Operation mode is normal or temporary disable mode. */ - if (hfs1.fields.working_state != ME_HFS_CWS_NORMAL || - (hfs1.fields.operation_mode != ME_HFS_MODE_NORMAL && - hfs1.fields.operation_mode != ME_HFS_TEMP_DISABLE)) { + if (hfs1.fields.working_state != ME_HFS1_CWS_NORMAL || + (hfs1.fields.operation_mode != ME_HFS1_COM_NORMAL && + hfs1.fields.operation_mode != ME_HFS1_COM_SOFT_TEMP_DISABLE)) { printk(BIOS_ERR, "HECI: ME not in required Mode\n"); goto failed; } @@ -697,7 +680,7 @@
struct hmrfpo_get_status_msg msg = { .hdr = { - .group_id = MKHI_HMRFPO_GROUP_ID, + .group_id = MKHI_GROUP_ID_HMRFPO, .command = MKHI_HMRFPO_GET_STATUS, }, }; diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index b4bfe68..751c01d 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -19,6 +19,28 @@
#include <stdint.h>
+/* MKHI Command groups */ +#define MKHI_GROUP_ID_CBM 0x0 +#define MKHI_GROUP_ID_HMRFPO 0x5 + +/* Global Reset Command ID */ +#define MKHI_CBM_GLOBAL_RESET_REQ 0xb + +/* RST Origin */ +#define GR_ORIGIN_BIOS_POST 0x2 + +/* HMRFPO Command Ids */ +#define MKHI_HMRFPO_ENABLE 0x1 +#define MKHI_HMRFPO_GET_STATUS 0x3 + +/* ME Current Working States */ +#define ME_HFS1_CWS_NORMAL 0x5 + +/* ME Current Operation Modes */ +#define ME_HFS1_COM_NORMAL 0x0 +#define ME_HFS1_COM_SOFT_TEMP_DISABLE 0x3 +#define ME_HFS1_COM_SECOVER_MEI_MSG 0x5 + /* HFSTS register offsets in PCI config space */ enum { PCI_ME_HFSTS1 = 0x40,
-
Furquan Shaikh (Code Review) -
Patrick Georgi (Code Review)
-
Sridhar Siricilla (Code Review)