[S] Change in coreboot[master]: soc/intel/tigerlake: Replace TcssD3ColdDisable with D3COLD_SUPPORT

[Lean Sheng Tan (Code Review)]

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74476 )

(

3 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
 )Change subject: soc/intel/tigerlake: Replace TcssD3ColdDisable with D3COLD_SUPPORT
......................................................................

soc/intel/tigerlake: Replace TcssD3ColdDisable with D3COLD_SUPPORT

Remove the `TcssD3ColdDisable` option in devicetree, as it exists
in Kconfig. The setting is only used on `starlabs/starbook` which
selects D3COLD_SUPPORT so the UPDs will not change.

Signed-off-by: Sean Rhodes 
Change-Id: I50e49e900c96748edd5b678765e47cc0e0d9b280
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74476
Reviewed-by: Nico Huber 
Reviewed-by: Michael Niewöhner 
Tested-by: build bot (Jenkins) 
---
M src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb
M src/mainboard/starlabs/starbook/variants/tgl/devtree.c
M src/soc/intel/tigerlake/chip.h
M src/soc/intel/tigerlake/fsp_params.c
4 files changed, 19 insertions(+), 5 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Nico Huber: Looks good to me, but someone else must approve
  Michael Niewöhner: Looks good to me, approved

diff --git a/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb
index cd8c480..c3a3f45 100644
--- a/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb
@@ -19,7 +19,6 @@
    register "CnviBtAudioOffload"		= "1"
    register "enable_c6dram"		= "1"
    register "SaGv"				= "SaGv_Enabled"
-	register "TcssD3ColdDisable"		= "1"

# FSP Silicon
    # Serial I/O
diff --git a/src/mainboard/starlabs/starbook/variants/tgl/devtree.c b/src/mainboard/starlabs/starbook/variants/tgl/devtree.c
index 1c280c4..0077a63 100644
--- a/src/mainboard/starlabs/starbook/variants/tgl/devtree.c
+++ b/src/mainboard/starlabs/starbook/variants/tgl/devtree.c
@@ -60,7 +60,6 @@
    if (get_uint_option("thunderbolt", 1) == 0) {
    	cfg->UsbTcPortEn = 0;
    	cfg->TcssXhciEn = 0;
-		cfg->TcssD3ColdDisable = 0;
    	tbt_pci_dev->enabled = 0;
    	tbt_dma_dev->enabled = 0;
    }
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index 6aa0408..3de8ffa 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -148,8 +148,6 @@

/* Support for TCSS xhci, xdci, TBT PCIe root ports and DMA controllers */
    uint8_t TcssD3HotDisable;
-	/* Support for TBT PCIe root ports and DMA controllers with D3Hot->D3Cold */
-	uint8_t TcssD3ColdDisable;

/* Enable DPTF support */
    int dptf_enable;
diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c
index b823f50..358536e 100644
--- a/src/soc/intel/tigerlake/fsp_params.c
+++ b/src/soc/intel/tigerlake/fsp_params.c
@@ -327,7 +327,7 @@
    if (cpu_id == CPUID_TIGERLAKE_A0)
    	params->D3ColdEnable = 0;
    else
-		params->D3ColdEnable = !config->TcssD3ColdDisable;
+		params->D3ColdEnable = CONFIG(D3COLD_SUPPORT);

params->UsbTcPortEn = config->UsbTcPortEn;
    params->TcssAuxOri = config->TcssAuxOri;