[XS] Change in coreboot[main]: soc/amd/glinda: Adding SPI controller to ACPI

[Ana Carolina Cabral (Code Review)]

Ana Carolina Cabral has posted comments on this change by Ana Carolina Cabral. ( https://review.coreboot.org/c/coreboot/+/84643?usp=email )

Change subject: soc/amd/glinda: Adding SPI controller to ACPI
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Patch Set 3:

(7 comments)

This change is ready for review.

Commit Message:

https://review.coreboot.org/c/coreboot/+/84643/comment/968baf1a_438d109d?usp... :
PS2, Line 7: soc/amd/glinda: SPI DEV entries missing in coreboot and UEFI BIOS
> Please make the statement about the action of the change and not an issue description.

Done

https://review.coreboot.org/c/coreboot/+/84643/comment/af718a88_4b43aa11?usp... :
PS2, Line 8:
> Please describe the problem, and then the fix.

Done

File src/soc/amd/glinda/acpi/soc.asl:

https://review.coreboot.org/c/coreboot/+/84643/comment/5f98285d_9dedafc7?usp... :
PS2, Line 22: 	#include "spi.asl"
> since the spi controller is an mmio device, i'd probably include the corresponding file from the soc […]

Done

File src/soc/amd/glinda/acpi/spi.asl:

PS2:
> only had a very brief look, but this should probably end up in the common amd soc code

Done

https://review.coreboot.org/c/coreboot/+/84643/comment/b321240e_68f38bf3?usp... :
PS2, Line 19: 0xFEC10000
> this is SPI_BASE_ADDRESS from soc/iomap. […]

Done

https://review.coreboot.org/c/coreboot/+/84643/comment/9204ade2_d2a6bfc5?usp... :
PS2, Line 23: 0x22
> SPI100_SPEED_CONFIG; would probably require some preprocessor magic to only include the parts of the […]

Done

https://review.coreboot.org/c/coreboot/+/84643/comment/1385ce21_4cebcc15?usp... :
PS2, Line 25: 0xFC
> SPI_MISC_CNTRL; would probably require some preprocessor magic to only include the parts of the head […]

Done