[S] Change in coreboot[master]: soc/amd/common/block/acpi/ivrs: conditionally generate eMMC entry

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75933?usp=email )

Change subject: soc/amd/common/block/acpi/ivrs: conditionally generate eMMC entry
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soc/amd/common/block/acpi/ivrs: conditionally generate eMMC entry

The eMMC entry in the IVRS table should only be generated if an eMMC
controller is present in the SoC.

Where the PCI_DEVFN(0x13, 1) is from is currently unclear to me. There
is no PCI device 0x13 on bus 0 and the eMMC controller is also an MMIO
device and not a PCI device, but this is what the reference code does.
My guess would be that it mainly needs to be a unique PCI device that
won't collide with any existing PCI device in the SoC. Add a comment
about this too.

TEST=None

Signed-off-by: Felix Held 
Change-Id: I00865cb7caf82547e89eb5e77817e3d8ca5d35dd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75933
Tested-by: build bot (Jenkins) 
Reviewed-by: Fred Reitberger 
---
M src/soc/amd/common/block/acpi/ivrs.c
1 file changed, 9 insertions(+), 4 deletions(-)

Approvals:
  Fred Reitberger: Looks good to me, approved
  build bot (Jenkins): Verified

diff --git a/src/soc/amd/common/block/acpi/ivrs.c b/src/soc/amd/common/block/acpi/ivrs.c
index 7f1fe5d..79b4ff6 100644
--- a/src/soc/amd/common/block/acpi/ivrs.c
+++ b/src/soc/amd/common/block/acpi/ivrs.c
@@ -245,10 +245,15 @@

if (nb_dev->bus->secondary == 0) {
    	/* Describe EMMC */
-		current = ivhd_describe_f0_device(current, PCI_DEVFN(0x13, 1),
-					IVHD_DTE_LINT_1_PASS | IVHD_DTE_LINT_0_PASS |
-					IVHD_DTE_SYS_MGT_TRANS   | IVHD_DTE_NMI_PASS |
-					IVHD_DTE_EXT_INT_PASS | IVHD_DTE_INIT_PASS);
+		if (CONFIG(SOC_AMD_COMMON_BLOCK_EMMC)) {
+			/* PCI_DEVFN(0x13, 1) doesn't exist in the hardware, but it's what the
+			 * reference code uses. Maybe to have a unique PCI device to put into
+			 * the field that doesn't collide with any existing device? */
+			current = ivhd_describe_f0_device(current, PCI_DEVFN(0x13, 1),
+						IVHD_DTE_LINT_1_PASS | IVHD_DTE_LINT_0_PASS |
+						IVHD_DTE_SYS_MGT_TRANS   | IVHD_DTE_NMI_PASS |
+						IVHD_DTE_EXT_INT_PASS | IVHD_DTE_INIT_PASS);
+		}
    }
    ivhd_40->length += (current - current_backup);