Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31908
Change subject: soc/intel/cannonlake: Fix GEN_PMCON bit checks ......................................................................
soc/intel/cannonlake: Fix GEN_PMCON bit checks
CNL PCH has PWR_FLR, SUS_PWR_FLR and HOST_RST_STS bits in GEN_PMCON_A and so this change updates the check for these bits to use GEN_PMCON_A instead of GEN_PMCON_B.
BUG=b:128482282 TEST=Verified that prev_sleep_state is reported correctly when booting from S5.
Change-Id: I75780a004ded8f282ffb3feb0cdc76233ebfd4f2 Signed-off-by: Furquan Shaikh furquan@google.com --- M src/soc/intel/cannonlake/elog.c M src/soc/intel/cannonlake/pmutil.c 2 files changed, 5 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/31908/1
diff --git a/src/soc/intel/cannonlake/elog.c b/src/soc/intel/cannonlake/elog.c index 5319cff..2ec6b41 100644 --- a/src/soc/intel/cannonlake/elog.c +++ b/src/soc/intel/cannonlake/elog.c @@ -76,11 +76,11 @@ elog_add_event(ELOG_TYPE_THERM_TRIP);
/* PWR_FLR Power Failure */ - if (ps->gen_pmcon_b & PWR_FLR) + if (ps->gen_pmcon_a & PWR_FLR) elog_add_event(ELOG_TYPE_POWER_FAIL);
/* SUS Well Power Failure */ - if (ps->gen_pmcon_b & SUS_PWR_FLR) + if (ps->gen_pmcon_a & SUS_PWR_FLR) elog_add_event(ELOG_TYPE_SUS_POWER_FAIL);
/* TCO Timeout */ @@ -97,7 +97,7 @@ elog_add_event(ELOG_TYPE_RTC_RESET);
/* Host Reset Status */ - if (ps->gen_pmcon_b & HOST_RST_STS) + if (ps->gen_pmcon_a & HOST_RST_STS) elog_add_event(ELOG_TYPE_SYSTEM_RESET);
/* ACPI Wake Event */ diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c index 16c4db6..8c166cf 100644 --- a/src/soc/intel/cannonlake/pmutil.c +++ b/src/soc/intel/cannonlake/pmutil.c @@ -217,7 +217,7 @@ * S5 because the PCH does not set the WAK_STS bit when waking * from a true G3 state. */ - if (ps->gen_pmcon_b & (PWR_FLR | SUS_PWR_FLR)) + if (ps->gen_pmcon_a & (PWR_FLR | SUS_PWR_FLR)) prev_sleep_state = ACPI_S5;
/* @@ -233,7 +233,7 @@ if (!deep_s3_enabled()) mask |= SUS_PWR_FLR;
- if (ps->gen_pmcon_b & mask) + if (ps->gen_pmcon_a & mask) prev_sleep_state = ACPI_S5; }
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31908 )
Change subject: soc/intel/cannonlake: Fix GEN_PMCON bit checks ......................................................................
Patch Set 1: Code-Review+2
Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31908 )
Change subject: soc/intel/cannonlake: Fix GEN_PMCON bit checks ......................................................................
Patch Set 1: Code-Review+2
Furquan Shaikh has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31908 )
Change subject: soc/intel/cannonlake: Fix GEN_PMCON bit checks ......................................................................
soc/intel/cannonlake: Fix GEN_PMCON bit checks
CNL PCH has PWR_FLR, SUS_PWR_FLR and HOST_RST_STS bits in GEN_PMCON_A and so this change updates the check for these bits to use GEN_PMCON_A instead of GEN_PMCON_B.
BUG=b:128482282 TEST=Verified that prev_sleep_state is reported correctly when booting from S5.
Change-Id: I75780a004ded8f282ffb3feb0cdc76233ebfd4f2 Signed-off-by: Furquan Shaikh furquan@google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/31908 Reviewed-by: Aaron Durbin adurbin@chromium.org Reviewed-by: Duncan Laurie dlaurie@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/cannonlake/elog.c M src/soc/intel/cannonlake/pmutil.c 2 files changed, 5 insertions(+), 5 deletions(-)
Approvals: build bot (Jenkins): Verified Duncan Laurie: Looks good to me, approved Aaron Durbin: Looks good to me, approved
diff --git a/src/soc/intel/cannonlake/elog.c b/src/soc/intel/cannonlake/elog.c index 5319cff..2ec6b41 100644 --- a/src/soc/intel/cannonlake/elog.c +++ b/src/soc/intel/cannonlake/elog.c @@ -76,11 +76,11 @@ elog_add_event(ELOG_TYPE_THERM_TRIP);
/* PWR_FLR Power Failure */ - if (ps->gen_pmcon_b & PWR_FLR) + if (ps->gen_pmcon_a & PWR_FLR) elog_add_event(ELOG_TYPE_POWER_FAIL);
/* SUS Well Power Failure */ - if (ps->gen_pmcon_b & SUS_PWR_FLR) + if (ps->gen_pmcon_a & SUS_PWR_FLR) elog_add_event(ELOG_TYPE_SUS_POWER_FAIL);
/* TCO Timeout */ @@ -97,7 +97,7 @@ elog_add_event(ELOG_TYPE_RTC_RESET);
/* Host Reset Status */ - if (ps->gen_pmcon_b & HOST_RST_STS) + if (ps->gen_pmcon_a & HOST_RST_STS) elog_add_event(ELOG_TYPE_SYSTEM_RESET);
/* ACPI Wake Event */ diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c index 16c4db6..8c166cf 100644 --- a/src/soc/intel/cannonlake/pmutil.c +++ b/src/soc/intel/cannonlake/pmutil.c @@ -217,7 +217,7 @@ * S5 because the PCH does not set the WAK_STS bit when waking * from a true G3 state. */ - if (ps->gen_pmcon_b & (PWR_FLR | SUS_PWR_FLR)) + if (ps->gen_pmcon_a & (PWR_FLR | SUS_PWR_FLR)) prev_sleep_state = ACPI_S5;
/* @@ -233,7 +233,7 @@ if (!deep_s3_enabled()) mask |= SUS_PWR_FLR;
- if (ps->gen_pmcon_b & mask) + if (ps->gen_pmcon_a & mask) prev_sleep_state = ACPI_S5; }
-
Aaron Durbin (Code Review) -
Duncan Laurie (Code Review)
-
Furquan Shaikh (Code Review)