Change in coreboot[master]: soc/cavium/cn81xx: Fix minor things

[Philipp Deppenwiese (Code Review)]

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/27955 )

Change subject: soc/cavium/cn81xx: Fix minor things
......................................................................

soc/cavium/cn81xx: Fix minor things

* Move cbmem.c to cn81xx folder
* Store CBMEM below 4 GiB
* Make sure CBMEM doesn't overlap with ATF scratchpad
* Fix ATF scratchpad not marked as reserved due to wrong calculation
* The scratchpad is the last 1 MiB at the end of DRAM.

Tested on Cavium CN81xx EVB:
The ATF scratchpad is now marked reserved and the configuration tables
are located below 4 GiB. Linux still boots.

Change-Id: Ibbc8b586f04bd6867c045f5546b32a77c057ac74
Signed-off-by: Patrick Rudolph 
Reviewed-on: https://review.coreboot.org/27955
Reviewed-by: Philipp Deppenwiese 
Reviewed-by: Paul Menzel 
Tested-by: build bot (Jenkins) 
---
M src/soc/cavium/cn81xx/Makefile.inc
R src/soc/cavium/cn81xx/cbmem.c
M src/soc/cavium/cn81xx/soc.c
M src/soc/cavium/common/Makefile.inc
4 files changed, 8 insertions(+), 14 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Paul Menzel: Looks good to me, but someone else must approve
  Philipp Deppenwiese: Looks good to me, approved

diff --git a/src/soc/cavium/cn81xx/Makefile.inc b/src/soc/cavium/cn81xx/Makefile.inc
index 845ac34..2179bc7 100644
--- a/src/soc/cavium/cn81xx/Makefile.inc
+++ b/src/soc/cavium/cn81xx/Makefile.inc
@@ -39,16 +39,11 @@
 romstage-y += spi.c
 romstage-y += uart.c
 romstage-$(CONFIG_DRIVERS_UART) += uart.c
-romstage-< += cpu.c
+romstage-y += cbmem.c

romstage-y += sdram.c
 romstage-y += mmu.c

-romstage-y += ../common/cbmem.c
-# BDK coreboot interface
-romstage-y += ../common/bdk-coreboot.c
-
-
 ################################################################################
 # ramstage

@@ -64,12 +59,10 @@
 ramstage-y += cpu.c
 ramstage-y += cpu_secondary.S
 ramstage-y += ecam0.c
+ramstage-y += cbmem.c

ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += bl31_plat_params.c

-# BDK coreboot interface
-ramstage-y += ../common/bdk-coreboot.c
-
 BL31_MAKEARGS += PLAT=t81 M0_CROSS_COMPILE="$(CROSS_COMPILE_arm)" ENABLE_SPE_FOR_LOWER_ELS=0

CPPFLAGS_common += -Isrc/soc/cavium/cn81xx/include
diff --git a/src/soc/cavium/common/cbmem.c b/src/soc/cavium/cn81xx/cbmem.c
similarity index 82%
rename from src/soc/cavium/common/cbmem.c
rename to src/soc/cavium/cn81xx/cbmem.c
index 401f8b2..397fd26 100644
--- a/src/soc/cavium/common/cbmem.c
+++ b/src/soc/cavium/cn81xx/cbmem.c
@@ -21,6 +21,7 @@

void *cbmem_top(void)
 {
-	return (void *)min((uintptr_t)_dram + sdram_size_mb() * MiB,
-			   MAX_DRAM_ADDRESS);
+	/* Make sure not to overlap with reserved ATF scratchpad */
+	return (void *)min((uintptr_t)_dram + (sdram_size_mb() - 1) * MiB,
+			   4ULL * GiB);
 }
diff --git a/src/soc/cavium/cn81xx/soc.c b/src/soc/cavium/cn81xx/soc.c
index b575ca4..8efcb13 100644
--- a/src/soc/cavium/cn81xx/soc.c
+++ b/src/soc/cavium/cn81xx/soc.c
@@ -309,7 +309,8 @@
    		  BM_MEM_RESERVED);

/* Scratchpad for ATF SATA quirks */
-	bootmem_add_range(sdram_size_mb() * KiB, 1 * MiB, BM_MEM_RESERVED);
+	bootmem_add_range((sdram_size_mb() - 1) * MiB, 1 * MiB,
+			  BM_MEM_RESERVED);
 }

static void soc_read_resources(device_t dev)
diff --git a/src/soc/cavium/common/Makefile.inc b/src/soc/cavium/common/Makefile.inc
index 7af8bf5..ada8286 100644
--- a/src/soc/cavium/common/Makefile.inc
+++ b/src/soc/cavium/common/Makefile.inc
@@ -22,13 +22,12 @@
 ################################################################################
 # romstage

-romstage-y += cbmem.c
 romstage-y += bdk-coreboot.c

################################################################################
 # ramstage

-ramstage-y += cbmem.c
+ramstage-y += bdk-coreboot.c

CPPFLAGS_common += -Isrc/soc/cavium/common/include