[S] Change in coreboot[master]: mb/siemens/mc_ehl: Add FIVR config to devicetree for all variants

[Werner Zeh (Code Review)]

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68666 )

Change subject: mb/siemens/mc_ehl: Add FIVR config to devicetree for all variants
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mb/siemens/mc_ehl: Add FIVR config to devicetree for all variants

Add a config for FIVR in devicetree for both, mc_ehl1 and mc_ehl2
variants in order to provide the real delay value for the VCC supply
rail. This delay is needed to enable proper switching between different
VCC levels based on current system state.

Change-Id: Ibccb8ea1b42ccd2ff0a37cbd9651528a2a55ebd6
Signed-off-by: Werner Zeh 
---
M src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
2 files changed, 28 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/68666/1

diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
index 69277a5..44a1c38 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
@@ -126,6 +126,13 @@
    register "PchTsnGbeLinkSpeed" = "Tsn_2_5_Gbps"
    register "PchTsnGbeSgmiiEnable" = "1"

+	# FIVR related settings
+	register "fivr" = "{
+		.fivr_config_en = true,
+		.vcc_low_high_us = 50,
+	}"
+
+
    device domain 0 on
    	device pci 00.0 on	end # Host Bridge
    	device pci 02.0 on	end # Integrated Graphics Device
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
index ecf5d55..4109ec9 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
@@ -117,6 +117,12 @@
    	},
    }"

+	# FIVR related settings
+	register "fivr" = "{
+		.fivr_config_en = true,
+		.vcc_low_high_us = 50,
+	}"
+
    device domain 0 on
    	device pci 00.0 on	end # Host Bridge
    	device pci 02.0 on	end # Integrated Graphics Device