Shaunak Saha has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42557 )
Change subject: [WIP]mb/google/volteer: Disable CPU PCIE in FSP ......................................................................
[WIP]mb/google/volteer: Disable CPU PCIE in FSP
Signed-off-by: Shaunak Saha shaunak.saha@intel.com Change-Id: I7e8512d22b1463bc4207f80b16dcfb5d00ef4b46 --- M src/soc/intel/tigerlake/romstage/fsp_params.c 1 file changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/42557/1
diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c index f7956c8..b18cb53 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -196,6 +196,8 @@
/* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */ m_cfg->VmxEnable = CONFIG(ENABLE_VMX); + + m_cfg->CpuPcieRpEnableMask = 0; }
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42557 )
Change subject: [WIP]mb/google/volteer: Disable CPU PCIE in FSP ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42557/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42557/1//COMMIT_MSG@8 PS1, Line 8: Please add the reasoning to the commit message.
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42557
to look at the new patch set (#2).
Change subject: soc/intel/tigerlake: Disable CPU PCIE in FSP ......................................................................
soc/intel/tigerlake: Disable CPU PCIE in FSP
In TGL soc we have PCH and CPU side Pcie support. For Volteer and TGL RVP we are not using CPU side Pcie. This patch disables the initialization of CPU Pcie and hence saves ~30ms in FspSiliconInit.
BUG=b:158573805 BRANCH=None TEST=Build and boot volteer and TGL RVP. Using cbmem tool measure the boot time. FspSilicontInit time is reduced by ~30ms with this patch.
Signed-off-by: Shaunak Saha shaunak.saha@intel.com Change-Id: I7e8512d22b1463bc4207f80b16dcfb5d00ef4b46 --- M src/soc/intel/tigerlake/romstage/fsp_params.c 1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/42557/2
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42557
to look at the new patch set (#3).
Change subject: soc/intel/tigerlake: Disable CPU PCIE in FSP ......................................................................
soc/intel/tigerlake: Disable CPU PCIE in FSP
iIn TGL soc we have PCH and CPU side Pcie support. For Volteer and TGL RVP we are not using CPU side Pcie. This patch disables the initialization of CPU Pcie and hence saves ~30ms in FspSiliconInit.
BUG=b:158573805 BRANCH=None TEST=Build and boot volteer and TGL RVP. Using cbmem tool measure the boot time. FspSilicontInit time is reduced by ~30ms with this patch.
Signed-off-by: Shaunak Saha shaunak.saha@intel.com Change-Id: I7e8512d22b1463bc4207f80b16dcfb5d00ef4b46 --- M src/soc/intel/tigerlake/romstage/fsp_params.c 1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/42557/3
Shaunak Saha has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42557 )
Change subject: soc/intel/tigerlake: Disable CPU PCIE in FSP ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42557/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42557/1//COMMIT_MSG@8 PS1, Line 8:
Please add the reasoning to the commit message.
Sure. Will do.
Shaunak Saha has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42557 )
Change subject: soc/intel/tigerlake: Disable CPU PCIE in FSP ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42557/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42557/1//COMMIT_MSG@8 PS1, Line 8:
Sure. Will do.
Done
Shaunak Saha has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42557 )
Change subject: soc/intel/tigerlake: Disable CPU PCIE in FSP ......................................................................
Patch Set 3: Code-Review-1
Keeping it -1 till we do proper testing on all the sku's
Shaunak Saha has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42557 )
Change subject: soc/intel/tigerlake: Disable CPU PCIE in FSP ......................................................................
Patch Set 3: -Code-Review
Shaunak Saha has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42557 )
Change subject: soc/intel/tigerlake: Disable CPU PCIE in FSP ......................................................................
Patch Set 3: Code-Review-1
Shaunak Saha has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42557 )
Change subject: soc/intel/tigerlake: Disable CPU PCIE in FSP ......................................................................
Patch Set 3: Code-Review+1
Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42557 )
Change subject: soc/intel/tigerlake: Disable CPU PCIE in FSP ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42557/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42557/3//COMMIT_MSG@9 PS3, Line 9: iIn In?
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42557 )
Change subject: soc/intel/tigerlake: Disable CPU PCIE in FSP ......................................................................
Patch Set 3:
(4 comments)
https://review.coreboot.org/c/coreboot/+/42557/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42557/3//COMMIT_MSG@10 PS3, Line 10: Pcie PCIe
https://review.coreboot.org/c/coreboot/+/42557/3//COMMIT_MSG@11 PS3, Line 11: Pcie PCIe
https://review.coreboot.org/c/coreboot/+/42557/3//COMMIT_MSG@11 PS3, Line 11: hence saves ~30ms in : FspSiliconInit. Nice!
https://review.coreboot.org/c/coreboot/+/42557/3//COMMIT_MSG@18 PS3, Line 18: this patch. Fits on the line above?
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42557 )
Change subject: soc/intel/tigerlake: Disable CPU PCIE in FSP ......................................................................
Patch Set 3:
(5 comments)
a
https://review.coreboot.org/c/coreboot/+/42557/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42557/3//COMMIT_MSG@7 PS3, Line 7: PCIE PCIe
https://review.coreboot.org/c/coreboot/+/42557/3//COMMIT_MSG@9 PS3, Line 9: Pcie PCIe
https://review.coreboot.org/c/coreboot/+/42557/3//COMMIT_MSG@18 PS3, Line 18: this patch.
Fits on the line above?
Tiiight, but it does if split up like this:
TEST=Build and boot volteer and TGL RVP. Using cbmem tool measure the boot time. FspSilicontInit time is reduced by ~30ms with this patch.
https://review.coreboot.org/c/coreboot/+/42557/3/src/soc/intel/tigerlake/rom... File src/soc/intel/tigerlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/42557/3/src/soc/intel/tigerlake/rom... PS3, Line 207: Pcie PCIe
https://review.coreboot.org/c/coreboot/+/42557/3/src/soc/intel/tigerlake/rom... PS3, Line 208: 0 I would say someone will eventually use the CPU PCie root ports. Could you please expand the comment and mention which PCI devices (Bus:Dev.Function) are controlled by this UPD?
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42557 )
Change subject: soc/intel/tigerlake: Disable CPU PCIE in FSP ......................................................................
Patch Set 3:
Patch Set 3:
(5 comments)
a
Ha, I am not the only one, where there seems to be a condition, where the browser or Gerrit puts the command *a* into the comment.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42557 )
Change subject: soc/intel/tigerlake: Disable CPU PCIE in FSP ......................................................................
Patch Set 3:
(2 comments)
https://review.coreboot.org/c/coreboot/+/42557/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42557/3//COMMIT_MSG@9 PS3, Line 9: soc SoC
https://review.coreboot.org/c/coreboot/+/42557/3/src/soc/intel/tigerlake/rom... File src/soc/intel/tigerlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/42557/3/src/soc/intel/tigerlake/rom... PS3, Line 208: 0
I would say someone will eventually use the CPU PCie root ports. […]
Agreed, let's please add an option for this to `struct soc_intel_tigerlake_config` in the chip.h
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42557 )
Change subject: soc/intel/tigerlake: Disable CPU PCIE in FSP ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42557/3/src/soc/intel/tigerlake/rom... File src/soc/intel/tigerlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/42557/3/src/soc/intel/tigerlake/rom... PS3, Line 208: 0
Agreed, let's please add an option for this to `struct soc_intel_tigerlake_config` in the chip. […]
Well, if each bit corresponds to one PCI function, then we might as well check the corresponding devicetree devices and program this accordingly. Otherwise, the option would need to be manually kept in sync with the devicetree. I did something like that in CB:43128
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42557 )
Change subject: soc/intel/tigerlake: Disable CPU PCIE in FSP ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42557/3/src/soc/intel/tigerlake/rom... File src/soc/intel/tigerlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/42557/3/src/soc/intel/tigerlake/rom... PS3, Line 208: 0
Well, if each bit corresponds to one PCI function, then we might as well check the corresponding dev […]
Ok, looking back, TGL-U/Y seems to only has one CPU-side PCIe root port (00:06.00), so that would make sense to tie this to the device enabled state.
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42557 )
Change subject: soc/intel/tigerlake: Disable CPU PCIE in FSP ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42557/3/src/soc/intel/tigerlake/rom... File src/soc/intel/tigerlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/42557/3/src/soc/intel/tigerlake/rom... PS3, Line 208: 0
Ok, looking back, TGL-U/Y seems to only has one CPU-side PCIe root port (00:06. […]
Yes, that's correct. it's tide to 0.6.0 device and TGLU and TGLY only have 1 port(1x4).
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42557 )
Change subject: soc/intel/tigerlake: Disable CPU PCIE in FSP ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42557/3/src/soc/intel/tigerlake/rom... File src/soc/intel/tigerlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/42557/3/src/soc/intel/tigerlake/rom... PS3, Line 208: 0
Yes, that's correct. it's tide to 0.6.0 device and TGLU and TGLY only have 1 port(1x4).
Right, so it would be good to add that 0:6.0 device in `soc/pci_devs.h` and then do:
dev = pcidev_path_on_root(SA_DEVFN_CPU_PCIE); m_cfg->CpuPcieRpEnableMask = dev && dev->enabled;
Shaunak Saha has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42557 )
Change subject: soc/intel/tigerlake: Disable CPU PCIE in FSP ......................................................................
Patch Set 3:
(8 comments)
https://review.coreboot.org/c/coreboot/+/42557/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42557/3//COMMIT_MSG@7 PS3, Line 7: PCIE
PCIe
Will fix
https://review.coreboot.org/c/coreboot/+/42557/3//COMMIT_MSG@9 PS3, Line 9: iIn
In?
Will fix
https://review.coreboot.org/c/coreboot/+/42557/3//COMMIT_MSG@9 PS3, Line 9: Pcie
PCIe
Will fix
https://review.coreboot.org/c/coreboot/+/42557/3//COMMIT_MSG@9 PS3, Line 9: soc
SoC
Will fix
https://review.coreboot.org/c/coreboot/+/42557/3//COMMIT_MSG@10 PS3, Line 10: Pcie
PCIe
Will fix
https://review.coreboot.org/c/coreboot/+/42557/3//COMMIT_MSG@11 PS3, Line 11: Pcie
PCIe
Will fix
https://review.coreboot.org/c/coreboot/+/42557/3//COMMIT_MSG@18 PS3, Line 18: this patch.
Tiiight, but it does if split up like this: […]
Will fix
https://review.coreboot.org/c/coreboot/+/42557/3/src/soc/intel/tigerlake/rom... File src/soc/intel/tigerlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/42557/3/src/soc/intel/tigerlake/rom... PS3, Line 208: 0
Right, so it would be good to add that 0:6.0 device in `soc/pci_devs.h` and then do: […]
Thanks for the review. I will add 0:6.0 device in pci_devs.h and change this code to: dev = pcidev_path_on_root(SA_DEVFN_CPU_PCIE); m_cfg->CpuPcieRpEnableMask = dev && dev->enabled;
Hello build bot (Jenkins), Furquan Shaikh, Wonkyu Kim, Caveh Jalali, Ravishankar Sarawadi, Duncan Laurie, Nick Vaccaro, Tim Wawrzynczak, Srinidhi N Kaushik, Raj Astekar, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42557
to look at the new patch set (#4).
Change subject: soc/intel/tigerlake: Disable CPU PCIe in FSP ......................................................................
soc/intel/tigerlake: Disable CPU PCIe in FSP
In TGL SoC we have PCH and CPU side PCIe support. This patch skips CPU side PCIe enablemen in FSP if device is disabled in devicetree. Disabling the initialization of CPU PCIe saves ~30ms in FspSiliconInit.
BUG=b:158573805 BRANCH=None TEST=Build and boot volteer and TGL RVP. Using cbmem tool measure the boot time. FspSilicontInit time is reduced by ~30ms with this patch.
Signed-off-by: Shaunak Saha shaunak.saha@intel.com Change-Id: I7e8512d22b1463bc4207f80b16dcfb5d00ef4b46 --- M src/soc/intel/tigerlake/include/soc/pci_devs.h M src/soc/intel/tigerlake/romstage/fsp_params.c 2 files changed, 7 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/42557/4
Hello build bot (Jenkins), Furquan Shaikh, Wonkyu Kim, Caveh Jalali, Ravishankar Sarawadi, Duncan Laurie, Nick Vaccaro, Tim Wawrzynczak, Srinidhi N Kaushik, Raj Astekar, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42557
to look at the new patch set (#5).
Change subject: soc/intel/tigerlake: Disable CPU PCIe in FSP ......................................................................
soc/intel/tigerlake: Disable CPU PCIe in FSP
In TGL SoC we have PCH and CPU side PCIe support. This patch skips CPU side PCIe enablemen in FSP if device is disabled in devicetree. Disabling the initialization of CPU PCIe saves ~30ms in FspSiliconInit!
BUG=b:158573805 BRANCH=None TEST=Build and boot volteer and TGL RVP. Using cbmem tool measure the boot time. FspSilicontInit time is reduced by ~30ms with this patch.
Signed-off-by: Shaunak Saha shaunak.saha@intel.com Change-Id: I7e8512d22b1463bc4207f80b16dcfb5d00ef4b46 --- M src/soc/intel/tigerlake/include/soc/pci_devs.h M src/soc/intel/tigerlake/romstage/fsp_params.c 2 files changed, 7 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/42557/5
Shaunak Saha has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42557 )
Change subject: soc/intel/tigerlake: Disable CPU PCIe in FSP ......................................................................
Patch Set 5:
(9 comments)
https://review.coreboot.org/c/coreboot/+/42557/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42557/3//COMMIT_MSG@7 PS3, Line 7: PCIE
Will fix
Done
https://review.coreboot.org/c/coreboot/+/42557/3//COMMIT_MSG@9 PS3, Line 9: iIn
Will fix
Done
https://review.coreboot.org/c/coreboot/+/42557/3//COMMIT_MSG@9 PS3, Line 9: Pcie
Will fix
Done
https://review.coreboot.org/c/coreboot/+/42557/3//COMMIT_MSG@9 PS3, Line 9: soc
Will fix
Done
https://review.coreboot.org/c/coreboot/+/42557/3//COMMIT_MSG@10 PS3, Line 10: Pcie
Will fix
Done
https://review.coreboot.org/c/coreboot/+/42557/3//COMMIT_MSG@11 PS3, Line 11: Pcie
Will fix
Done
https://review.coreboot.org/c/coreboot/+/42557/3//COMMIT_MSG@18 PS3, Line 18: this patch.
Will fix
Done
https://review.coreboot.org/c/coreboot/+/42557/3/src/soc/intel/tigerlake/rom... File src/soc/intel/tigerlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/42557/3/src/soc/intel/tigerlake/rom... PS3, Line 207: Pcie
PCIe
Done
https://review.coreboot.org/c/coreboot/+/42557/3/src/soc/intel/tigerlake/rom... PS3, Line 208: 0
Thanks for the review. […]
Done
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42557 )
Change subject: soc/intel/tigerlake: Disable CPU PCIe in FSP ......................................................................
Patch Set 5: Code-Review+1
(12 comments)
https://review.coreboot.org/c/coreboot/+/42557/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42557/3//COMMIT_MSG@7 PS3, Line 7: PCIE
Will fix
Done
https://review.coreboot.org/c/coreboot/+/42557/3//COMMIT_MSG@9 PS3, Line 9: iIn
Will fix
Done
https://review.coreboot.org/c/coreboot/+/42557/3//COMMIT_MSG@9 PS3, Line 9: Pcie
Will fix
Done
https://review.coreboot.org/c/coreboot/+/42557/3//COMMIT_MSG@9 PS3, Line 9: soc
Will fix
Done
https://review.coreboot.org/c/coreboot/+/42557/3//COMMIT_MSG@10 PS3, Line 10: Pcie
Will fix
Done
https://review.coreboot.org/c/coreboot/+/42557/3//COMMIT_MSG@11 PS3, Line 11: Pcie
Will fix
Done
https://review.coreboot.org/c/coreboot/+/42557/3//COMMIT_MSG@18 PS3, Line 18: this patch.
Will fix
Welp, Gerrit broke my lines... I've put clearer comments on the latest patchset.
https://review.coreboot.org/c/coreboot/+/42557/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42557/5//COMMIT_MSG@10 PS5, Line 10: enablemen enablement
https://review.coreboot.org/c/coreboot/+/42557/5//COMMIT_MSG@17 PS5, Line 17: the this fits on the previous line
https://review.coreboot.org/c/coreboot/+/42557/5//COMMIT_MSG@19 PS5, Line 19: this patch. this fits on the previous line
https://review.coreboot.org/c/coreboot/+/42557/3/src/soc/intel/tigerlake/rom... File src/soc/intel/tigerlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/42557/3/src/soc/intel/tigerlake/rom... PS3, Line 207: Pcie
PCIe
Done
https://review.coreboot.org/c/coreboot/+/42557/3/src/soc/intel/tigerlake/rom... PS3, Line 208: 0
Thanks for the review. […]
Done
Hello build bot (Jenkins), Furquan Shaikh, Wonkyu Kim, Ravishankar Sarawadi, Duncan Laurie, Nick Vaccaro, Angel Pons, Tim Wawrzynczak, Patrick Rudolph, Caveh Jalali, Srinidhi N Kaushik, Raj Astekar,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42557
to look at the new patch set (#6).
Change subject: soc/intel/tigerlake: Disable CPU PCIe in FSP ......................................................................
soc/intel/tigerlake: Disable CPU PCIe in FSP
In TGL SoC we have PCH and CPU side PCIe support. This patch skips CPU side PCIe enablement in FSP if device is disabled in devicetree. Disabling the initialization of CPU PCIe saves ~30ms in FspSiliconInit!
BUG=b:158573805 BRANCH=None TEST=Build and boot volteer and TGL RVP. Using cbmem tool measure the boot time. FspSilicontInit time is reduced by ~30ms with this patch.
Signed-off-by: Shaunak Saha shaunak.saha@intel.com Change-Id: I7e8512d22b1463bc4207f80b16dcfb5d00ef4b46 --- M src/soc/intel/tigerlake/include/soc/pci_devs.h M src/soc/intel/tigerlake/romstage/fsp_params.c 2 files changed, 7 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/42557/6
Shaunak Saha has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42557 )
Change subject: soc/intel/tigerlake: Disable CPU PCIe in FSP ......................................................................
Patch Set 6:
(3 comments)
https://review.coreboot.org/c/coreboot/+/42557/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42557/5//COMMIT_MSG@10 PS5, Line 10: enablemen
enablement
Done
https://review.coreboot.org/c/coreboot/+/42557/5//COMMIT_MSG@17 PS5, Line 17: the
this fits on the previous line
Done
https://review.coreboot.org/c/coreboot/+/42557/5//COMMIT_MSG@19 PS5, Line 19: this patch.
this fits on the previous line
Done
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42557 )
Change subject: soc/intel/tigerlake: Disable CPU PCIe in FSP ......................................................................
Patch Set 6: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42557 )
Change subject: soc/intel/tigerlake: Disable CPU PCIe in FSP ......................................................................
soc/intel/tigerlake: Disable CPU PCIe in FSP
In TGL SoC we have PCH and CPU side PCIe support. This patch skips CPU side PCIe enablement in FSP if device is disabled in devicetree. Disabling the initialization of CPU PCIe saves ~30ms in FspSiliconInit!
BUG=b:158573805 BRANCH=None TEST=Build and boot volteer and TGL RVP. Using cbmem tool measure the boot time. FspSilicontInit time is reduced by ~30ms with this patch.
Signed-off-by: Shaunak Saha shaunak.saha@intel.com Change-Id: I7e8512d22b1463bc4207f80b16dcfb5d00ef4b46 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42557 Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org Reviewed-by: Angel Pons th3fanbus@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/tigerlake/include/soc/pci_devs.h M src/soc/intel/tigerlake/romstage/fsp_params.c 2 files changed, 7 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/soc/intel/tigerlake/include/soc/pci_devs.h b/src/soc/intel/tigerlake/include/soc/pci_devs.h index 82d8360..cfb70cd 100644 --- a/src/soc/intel/tigerlake/include/soc/pci_devs.h +++ b/src/soc/intel/tigerlake/include/soc/pci_devs.h @@ -34,6 +34,9 @@ #define SA_DEVFN_IPU PCI_DEVFN(SA_DEV_SLOT_IPU, 0) #define SA_DEV_IPU PCI_DEV(0, SA_DEV_SLOT_IPU, 0)
+#define SA_DEV_SLOT_CPU_PCIE 0x06 +#define SA_DEVFN_CPU_PCIE PCI_DEVFN(SA_DEV_SLOT_CPU_PCIE, 0) + #define SA_DEV_SLOT_TBT 0x07 #define SA_DEVFN_TBT(x) PCI_DEVFN(SA_DEV_SLOT_TBT, (x)) #define NUM_TBT_FUNCTIONS 4 diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c index 4a45fd4..b12faec 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -217,6 +217,10 @@
/* Skip CPU replacement check */ m_cfg->SkipCpuReplacementCheck = !config->CpuReplacementCheck; + + /* Skip CPU side PCIe enablement in FSP if device is disabled in devicetree */ + dev = pcidev_path_on_root(SA_DEVFN_CPU_PCIE); + m_cfg->CpuPcieRpEnableMask = dev && dev->enabled; }
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
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Angel Pons (Code Review) -
Caveh Jalali (Code Review)
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Patrick Georgi (Code Review)
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Paul Menzel (Code Review)
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Shaunak Saha (Code Review)
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Tim Wawrzynczak (Code Review)
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Wonkyu Kim (Code Review)