Change in coreboot[master]: cpu/intel/haswell: Add s0ix support

[Angel Pons (Code Review)]

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46924 )

Change subject: cpu/intel/haswell: Add s0ix support
......................................................................

cpu/intel/haswell: Add s0ix support

Backported from Broadwell. This only matters for ULT variants.

Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.

Change-Id: I91c6f937c09c9254a6f698f3a6fb6366364e3b2b
Signed-off-by: Angel Pons 
---
M src/cpu/intel/haswell/acpi.c
M src/cpu/intel/haswell/chip.h
2 files changed, 27 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/46924/1

diff --git a/src/cpu/intel/haswell/acpi.c b/src/cpu/intel/haswell/acpi.c
index 7c99df3..0f11e5f 100644
--- a/src/cpu/intel/haswell/acpi.c
+++ b/src/cpu/intel/haswell/acpi.c
@@ -14,6 +14,12 @@

#include <southbridge/intel/lynxpoint/pch.h>

+static int cstate_set_s0ix[3] = {
+	C_STATE_C1E,
+	C_STATE_C7S_LONG_LAT,
+	C_STATE_C10,
+};
+
 static int cstate_set_lp[3] = {
    C_STATE_C1E,
    C_STATE_C3,
@@ -94,6 +100,21 @@
    		ARRAY_SIZE(tss_table_coarse), tss_table_coarse);
 }

+static bool is_s0ix_enabled(void)
+{
+	if (!haswell_is_ult())
+		return false;
+
+	const struct device *lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC);
+
+	if (!lapic || !lapic->chip_info)
+		return false;
+
+	const struct cpu_intel_haswell_config *conf = lapic->chip_info;
+
+	return conf->s0ix_enable;
+}
+
 static void generate_C_state_entries(void)
 {
    acpi_cstate_t map[3];
@@ -111,7 +132,9 @@
    if (!cpu || !cpu->cstates)
    	return;

-	if (haswell_is_ult())
+	if (is_s0ix_enabled())
+		set = cstate_set_s0ix;
+	else if (haswell_is_ult())
    	set = cstate_set_lp;
    else
    	set = cstate_set_trad;
diff --git a/src/cpu/intel/haswell/chip.h b/src/cpu/intel/haswell/chip.h
index 16f1079..776e239 100644
--- a/src/cpu/intel/haswell/chip.h
+++ b/src/cpu/intel/haswell/chip.h
@@ -34,4 +34,7 @@
    int tcc_offset;		/* TCC Activation Offset */

struct cpu_vr_config vr_config;
+
+	/* Enable S0iX support */
+	bool s0ix_enable;
 };

[Angel Pons (Code Review)]

Hello build bot (Jenkins), Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/46924

to look at the new patch set (#6).

Change subject: cpu/intel/haswell: Add s0ix support
......................................................................

cpu/intel/haswell: Add s0ix support

Backported from Broadwell. This only matters for ULT variants.

Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.

Change-Id: I91c6f937c09c9254a6f698f3a6fb6366364e3b2b
Signed-off-by: Angel Pons 
---
M src/cpu/intel/haswell/acpi.c
M src/cpu/intel/haswell/chip.h
2 files changed, 27 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/46924/6

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46924 )

Change subject: cpu/intel/haswell: Add s0ix support
......................................................................

Patch Set 14:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/46924/comment/e6c7f2f2_59df40f6 
PS14, Line 11: Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.
N.B. this only means that non-ULT is unaffected by this change.

[Arthur Heymans (Code Review)]

Attention is currently required from:  Felix Singer, Nico Huber, Tim Wawrzynczak, Angel Pons, Michael Niewöhner.
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46924 )

Change subject: cpu/intel/haswell: Add s0ix support
......................................................................

Patch Set 16: Code-Review+1

[Patrick Georgi (Code Review)]

Attention is currently required from:  Felix Singer, Nico Huber, Tim Wawrzynczak, Angel Pons, Michael Niewöhner.
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46924 )

Change subject: cpu/intel/haswell: Add s0ix support
......................................................................

Patch Set 16: Code-Review+2

(1 comment)

Patchset:

PS16: 
Might be worth a mention what board has been tested to gain S0ix support with that.

[Angel Pons (Code Review)]

Attention is currently required from:  Felix Singer, Nico Huber, Tim Wawrzynczak, Michael Niewöhner.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46924 )

Change subject: cpu/intel/haswell: Add s0ix support
......................................................................

Patch Set 16:

(1 comment)

Patchset:

PS16:
> Might be worth a mention what board has been tested to gain S0ix support with that.

None of the Haswell boards use s0ix, but some Broadwell boards do. Since I'm going to unify Haswell and Broadwell, I need to add support for s0ix.

[Angel Pons (Code Review)]

Attention is currently required from:  Felix Singer, Nico Huber, Tim Wawrzynczak, Michael Niewöhner.
Hello  Felix Singer, build bot (Jenkins), Nico Huber, Patrick Georgi, Tim Wawrzynczak, Arthur Heymans, Michael Niewöhner, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/46924

to look at the new patch set (#17).

Change subject: cpu/intel/haswell: Add s0ix support
......................................................................

cpu/intel/haswell: Add s0ix support

Backport Broadwell's s0ix support to Haswell in preparation to unify
both platforms' CPU code. Note that only ULT variants support s0ix.

This option is currently unused, but will be put to use in subsequent
commits, when switching Broadwell mainboards to use Haswell's CPU code.

Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.

Change-Id: I91c6f937c09c9254a6f698f3a6fb6366364e3b2b
Signed-off-by: Angel Pons 
---
M src/cpu/intel/haswell/acpi.c
M src/cpu/intel/haswell/chip.h
2 files changed, 27 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/46924/17

[Angel Pons (Code Review)]

Attention is currently required from:  Felix Singer, Nico Huber, Tim Wawrzynczak, Michael Niewöhner.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46924 )

Change subject: cpu/intel/haswell: Add s0ix support
......................................................................

Patch Set 17:

(1 comment)

Patchset:

PS16:
> None of the Haswell boards use s0ix, but some Broadwell boards do. […]

I expanded the commit message to reflect this change is only necessary to unify Haswell and Broadwell

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46924 )

Change subject: cpu/intel/haswell: Add s0ix support
......................................................................

cpu/intel/haswell: Add s0ix support

Backport Broadwell's s0ix support to Haswell in preparation to unify
both platforms' CPU code. Note that only ULT variants support s0ix.

This option is currently unused, but will be put to use in subsequent
commits, when switching Broadwell mainboards to use Haswell's CPU code.

Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.

Change-Id: I91c6f937c09c9254a6f698f3a6fb6366364e3b2b
Signed-off-by: Angel Pons 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46924
Reviewed-by: Arthur Heymans 
Reviewed-by: Patrick Georgi 
Tested-by: build bot (Jenkins) 
---
M src/cpu/intel/haswell/acpi.c
M src/cpu/intel/haswell/chip.h
2 files changed, 27 insertions(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Patrick Georgi: Looks good to me, approved
  Arthur Heymans: Looks good to me, but someone else must approve

diff --git a/src/cpu/intel/haswell/acpi.c b/src/cpu/intel/haswell/acpi.c
index 7c99df3..0f11e5f 100644
--- a/src/cpu/intel/haswell/acpi.c
+++ b/src/cpu/intel/haswell/acpi.c
@@ -14,6 +14,12 @@

#include <southbridge/intel/lynxpoint/pch.h>

+static int cstate_set_s0ix[3] = {
+	C_STATE_C1E,
+	C_STATE_C7S_LONG_LAT,
+	C_STATE_C10,
+};
+
 static int cstate_set_lp[3] = {
    C_STATE_C1E,
    C_STATE_C3,
@@ -94,6 +100,21 @@
    		ARRAY_SIZE(tss_table_coarse), tss_table_coarse);
 }

+static bool is_s0ix_enabled(void)
+{
+	if (!haswell_is_ult())
+		return false;
+
+	const struct device *lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC);
+
+	if (!lapic || !lapic->chip_info)
+		return false;
+
+	const struct cpu_intel_haswell_config *conf = lapic->chip_info;
+
+	return conf->s0ix_enable;
+}
+
 static void generate_C_state_entries(void)
 {
    acpi_cstate_t map[3];
@@ -111,7 +132,9 @@
    if (!cpu || !cpu->cstates)
    	return;

-	if (haswell_is_ult())
+	if (is_s0ix_enabled())
+		set = cstate_set_s0ix;
+	else if (haswell_is_ult())
    	set = cstate_set_lp;
    else
    	set = cstate_set_trad;
diff --git a/src/cpu/intel/haswell/chip.h b/src/cpu/intel/haswell/chip.h
index 16f1079..776e239 100644
--- a/src/cpu/intel/haswell/chip.h
+++ b/src/cpu/intel/haswell/chip.h
@@ -34,4 +34,7 @@
    int tcc_offset;		/* TCC Activation Offset */

struct cpu_vr_config vr_config;
+
+	/* Enable S0iX support */
+	bool s0ix_enable;
 };