[S] Change in coreboot[master]: soc/intel/xeon_sp/spr: Add weak method to get memory capability

[Ziang Wang (Code Review)]

Attention is currently required from: Arthur Heymans, Christian Walter, Eric Lai, Felix Singer, Lean Sheng Tan, Nico Huber, Patrick Rudolph, Paul Menzel, Tim Chu, Ziang Wang.

Hello Arthur Heymans, Christian Walter, Eric Lai, Felix Singer, Johnny Lin, Lean Sheng Tan, Nico Huber, Patrick Rudolph, Paul Menzel, Tim Chu, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/75740?usp=email

to look at the new patch set (#10).

The following approvals got outdated and were removed:
Code-Review+1 by Eric Lai

Change subject: soc/intel/xeon_sp/spr: Add weak method to get memory capability
......................................................................

soc/intel/xeon_sp/spr: Add weak method to get memory capability

Memory capacity could be 4TB or 6TB on different SPR SKUs, instead of
setting it statically at SoC level, it is better using a weak function
that can be overrode by mainboard.

Change-Id: Ieb892d3b148291b35808d634d63b58b90d456767
Signed-off-by: Ziang Wang 
---
M src/soc/intel/xeon_sp/spr/include/soc/ddr.h
M src/soc/intel/xeon_sp/spr/romstage.c
2 files changed, 17 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/75740/10