Siyuan Wang (wangsiyuanbuaa@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3011
-gerrit
commit fcfc9f5ccb1720e754ff8fa79b24d5fd17c303e6 Author: Siyuan Wang wangsiyuanbuaa@gmail.com Date: Tue Apr 2 10:49:09 2013 +0800
AMD Thatcher: Fix PCIE link issues
1). Thatcher PCIE x8 slot is reverse order. Fix PortList to enable it. 2). Fix DdiList to detect DP monitor or HDMI monitor. 3). Disable unused port and clean up code in PlatformGnbPcie.c and devicetree.cb
Change-Id: I8524b6fc1b6cdc03ba92e7191186bfb0986767c8 Signed-off-by: Siyuan Wang SiYuan.Wang@amd.com Signed-off-by: Siyuan Wang wangsiyuanbuaa@gmail.com --- src/mainboard/amd/thatcher/PlatformGnbPcie.c | 80 +++++++++++++--------------- src/mainboard/amd/thatcher/devicetree.cb | 12 ++--- 2 files changed, 42 insertions(+), 50 deletions(-)
diff --git a/src/mainboard/amd/thatcher/PlatformGnbPcie.c b/src/mainboard/amd/thatcher/PlatformGnbPcie.c index 8ee6707..c9e4564 100644 --- a/src/mainboard/amd/thatcher/PlatformGnbPcie.c +++ b/src/mainboard/amd/thatcher/PlatformGnbPcie.c @@ -23,100 +23,79 @@ #include "heapManager.h" #include "PlatformGnbPcieComplex.h" #include "Filecode.h" +#include "Fch.h"
#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
PCIe_PORT_DESCRIPTOR PortList [] = { - /* PCIe port, Lanes 8:23, PCI Device Number 2 */ + /* PCIe port, Lanes 15:8, PCI Device Number 2, PCIE SLOT x8 */ { 0, /* Descriptor flags */ - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 23), + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 15, 8), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) }, - /* PCIe port, Lanes 16:23, PCI Device Number 3 */ + /* PCIe port, Lanes 16:23, PCI Device Number 3, Disabled */ { 0, /* Descriptor flags */ PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 16, 23), PCIE_PORT_DATA_INITIALIZER (PortDisabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) },
- /* PCIe port, Lanes 4, PCI Device Number 4, PCIE MINI0 */ + /* PCIe port, Lanes 4, PCI Device Number 4, LAN */ { 0, /* Descriptor flags */ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) },
- /* PCIe port, Lanes 5, PCI Device Number 5, PCIE MINI1 */ + /* PCIe port, Lanes 5, PCI Device Number 5, PCIE MINI0 */ { 0, /* Descriptor flags */ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) },
- /* PCIe port, Lanes 6, PCI Device Number 6, PCIE SLOT1, TODO: Disabled. */ + /* PCIe port, Lanes 6, PCI Device Number 6, PCIE MINI1 */ { 0, /* Descriptor flags */ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) },
- /* PCIe port, Lanes 7, PCI Device Number 7, LAN , TODO: not the last entry.*/ + /* PCIe port, Lanes 7, PCI Device Number 7, PortDisabled */ { - 0, /* Descriptor flags !!!IMPORTANT!!! Terminate last element of array */ + 0, /* Descriptor flags */ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), - PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) + PCIE_PORT_DATA_INITIALIZER (PortDisabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) },
-#if 1 - /* Initialize Port descriptor (PCIe port, Lanes ?, PCI Device Number 8, ...) */ + /* PCIe port, Lanes 0:3, PCI Device Number 8, Bridge to FCH */ { DESCRIPTOR_TERMINATE_LIST, /* Descriptor flags !!!IMPORTANT!!! Terminate last element of array */ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) }, -#endif };
PCIe_DDI_DESCRIPTOR DdiList [] = { - // DP0 to HDMI0/DP + // DP0 to HDMI0/DP0 { - 0, + 1, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27), - PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux1, Hdp1) + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) }, - // DP1 to FCH + // DP1 to HDMI1/DP1 { - 0, + 1, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 28, 31), - PCIE_DDI_DATA_INITIALIZER (ConnectorTypeNutmegDpToVga, Aux2, Hdp2) + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) }, - // DP2 to HDMI1/DP + // DP2 to MINI-DDI Card { - 0, -// PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 32, 38), + 1, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 32, 35), - //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeEDP, Aux3, Hdp3) - PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux3, Hdp3) - }, - // GFX Lane 15-12 - { - 0, - PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 12, 15), - PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux4, Hdp4) + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux3, Hdp3) }, - // GFX Lane 11-8 - { - 0, - PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 16, 19), - PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux5, Hdp5) - }, - // GFX Lane 7-4 - { - DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 20, 23), - PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux6, Hdp6) - } };
PCIe_COMPLEX_DESCRIPTOR Trinity = { @@ -151,6 +130,7 @@ OemCustomizeInitEarly ( VOID *TrinityPcieComplexListPtr; VOID *TrinityPciePortPtr; VOID *TrinityPcieDdiPtr; + UINT8 Value;
ALLOCATE_HEAP_PARAMS AllocHeapParams;
@@ -161,7 +141,7 @@ OemCustomizeInitEarly ( // AllocHeapParams.RequestedBufferSize = (sizeof (PCIe_COMPLEX_DESCRIPTOR) + sizeof (PCIe_PORT_DESCRIPTOR) * 7 + - sizeof (PCIe_DDI_DESCRIPTOR)) * 6; + sizeof (PCIe_DDI_DESCRIPTOR)) * 3;
AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; AllocHeapParams.Persist = HEAP_LOCAL_CACHE; @@ -192,12 +172,24 @@ OemCustomizeInitEarly (
LibAmdMemFill (TrinityPcieDdiPtr, 0, - sizeof (PCIe_DDI_DESCRIPTOR) * 6, + sizeof (PCIe_DDI_DESCRIPTOR) * 3, &InitEarly->StdHeader);
LibAmdMemCopy (TrinityPcieComplexListPtr, &Trinity, sizeof (PCIe_COMPLEX_DESCRIPTOR), &InitEarly->StdHeader); LibAmdMemCopy (TrinityPciePortPtr, &PortList[0], sizeof (PCIe_PORT_DESCRIPTOR) * 7, &InitEarly->StdHeader); - LibAmdMemCopy (TrinityPcieDdiPtr, &DdiList[0], sizeof (PCIe_DDI_DESCRIPTOR) * 6, &InitEarly->StdHeader); + + LibAmdMemRead (AccessWidth8, ACPI_MMIO_BASE + GPIO_BASE + 50, &Value, &InitEarly->StdHeader); + if (!(Value & 0x80)) { + DdiList[0].Ddi.ConnectorType = ConnectorTypeHDMI; + + } + + LibAmdMemRead (AccessWidth8, ACPI_MMIO_BASE + GPIO_BASE + 51, &Value, &InitEarly->StdHeader); + if (!(Value & 0x80)) { + DdiList[1].Ddi.ConnectorType = ConnectorTypeHDMI; + + } + LibAmdMemCopy (TrinityPcieDdiPtr, &DdiList[0], sizeof (PCIe_DDI_DESCRIPTOR) * 3, &InitEarly->StdHeader);
((PCIe_COMPLEX_DESCRIPTOR*)TrinityPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)TrinityPciePortPtr; ((PCIe_COMPLEX_DESCRIPTOR*)TrinityPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)TrinityPcieDdiPtr; diff --git a/src/mainboard/amd/thatcher/devicetree.cb b/src/mainboard/amd/thatcher/devicetree.cb index 69dc0f8..330ee6b 100644 --- a/src/mainboard/amd/thatcher/devicetree.cb +++ b/src/mainboard/amd/thatcher/devicetree.cb @@ -32,12 +32,12 @@ chip northbridge/amd/agesa/family15tn/root_complex device pci 0.0 on end # Root Complex device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX device pci 1.1 on end # Internal Multimedia - device pci 2.0 on end # PCIE SLOT0 x16 - device pci 3.0 on end # PCIE SLOT0 x16 - device pci 4.0 on end # PCIE MINI0 - device pci 5.0 on end # PCIE MINI1 - device pci 6.0 on end # PCIE Slot1 x1 - device pci 7.0 on end # LAN + device pci 2.0 on end # PCIE SLOT0 x8 + device pci 3.0 off end + device pci 4.0 on end # LAN + device pci 5.0 on end # PCIE MINI0 + device pci 6.0 on end # PCIE MINI1 + device pci 7.0 off end device pci 8.0 off end # NB/SB Link P2P bridge end #chip northbridge/amd/agesa/family15tn # PCI side of HT root complex
-
Siyuan Wang