[XS] Change in coreboot[main]: mb/google/nissa/var/riven: Set PCIe root port 4 speed to Gen2

[David Wu (Code Review)]

Attention is currently required from: David Wu, Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro.

Hello Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/85520?usp=email

to look at the new patch set (#5).

Change subject: mb/google/nissa/var/riven: Set PCIe root port 4 speed to Gen2
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mb/google/nissa/var/riven: Set PCIe root port 4 speed to Gen2

The issue does not occur on Karis due to different WIFI module type
with current projects, Karis is using M.2 (none solder down version).
The decision to set PCIe root port 4 speed to Gen2 is based on experiment setup for b/374205496 and analysis results in #102.

BUG=b:374205496
TEST=Boot to OS and then check link speed.
     Use command: lspci -vv | grep 'LnkSta'

Before
     LnkSta: Speed 8GT/s (downgraded), Width x1
     After
     LnkSta: Speed 5GT/s (downgraded), Width x1

Change-Id: Ife2b60e78f943545fabd7095bd00d22704587aba
Signed-off-by: David Wu 
---
M src/mainboard/google/brya/variants/riven/overridetree.cb
1 file changed, 1 insertion(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/85520/5