the following patch was just integrated into master: commit bc07f5d93552640793254ce003937ec646120a21 Author: Aaron Durbin adurbin@chromium.org Date: Tue Mar 26 13:09:39 2013 -0500
x86: add rom cache variable MTRR index to tables
Downstream payloads may need to take advantage of caching the ROM for performance reasons. Add the ability to communicate the variable range MTRR index to use to perform the caching enablement.
An example usage implementation would be to obtain the variable MTRR index that covers the ROM from the coreboot tables. Then one would disable caching and change the MTRR type from uncacheable to write-protect and enable caching. The opposite sequence is required to tearn down the caching.
Change-Id: I4d486cfb986629247ab2da7818486973c6720ef5 Signed-off-by: Aaron Durbin adurbin@chromium.org Reviewed-on: http://review.coreboot.org/2919 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer stefan.reinauer@coreboot.org
Build-Tested: build bot (Jenkins) at Fri Mar 29 14:48:13 2013, giving +1 Reviewed-By: Stefan Reinauer stefan.reinauer@coreboot.org at Fri Mar 29 20:09:36 2013, giving +2 See http://review.coreboot.org/2919 for details.
-gerrit