the following patch was just integrated into master: commit 24de342438208d9b843e87627f15b9a272285b0f Author: Duncan Laurie dlaurie@chromium.org Date: Mon Sep 19 17:24:55 2016 -0700
mainboard/google/reef: Enable cr50 TPM interrupt
Enable the cr50 TPM and interrupt as GPE0_DW1_28 for use during verstage. The interrupt is left in APIC mode as the GPE is still latched when the GPIO is pulled low.
BUG=chrome-os-partner:53336
Change-Id: I28ade5ee3bf08fa17d8cabf16287319480f03921 Signed-off-by: Duncan Laurie dlaurie@chromium.org
See https://review.coreboot.org/16661 for details.
-gerrit