Change in coreboot[master]: soc/amd/picasso/cpu.c: Make comment clearer

[Raul Rangel (Code Review)]

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42108 )

Change subject: soc/amd/picasso/cpu.c: Make comment clearer
......................................................................

soc/amd/picasso/cpu.c: Make comment clearer

Explain why the flash is no longer cached.

BUG=none
TEST=none

Signed-off-by: Raul E Rangel 
Change-Id: Ibb18f363a215d665d53a722ed76896a75d1c5608
---
M src/soc/amd/picasso/cpu.c
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/42108/1

diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c
index 3512c94..de9a2fa 100644
--- a/src/soc/amd/picasso/cpu.c
+++ b/src/soc/amd/picasso/cpu.c
@@ -98,7 +98,7 @@
    if (mp_init_with_smm(cpu_bus, &mp_ops) < 0)
    	printk(BIOS_ERR, "MP initialization failure.\n");

-	/* The flash is now no longer cacheable. Reset to WP for performance. */
+	/* pre_mp_init made the flash not cacheable. Reset to WP for performance. */
    mtrr_use_temp_range(FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT);

set_warm_reset_flag();

[Aaron Durbin (Code Review)]

Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42108 )

Change subject: soc/amd/picasso/cpu.c: Make comment clearer
......................................................................

Patch Set 1: Code-Review+2

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42108 )

Change subject: soc/amd/picasso/cpu.c: Make comment clearer
......................................................................

Patch Set 1: Code-Review+2

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42108 )

Change subject: soc/amd/picasso/cpu.c: Make comment clearer
......................................................................

soc/amd/picasso/cpu.c: Make comment clearer

Explain why the flash is no longer cached.

BUG=none
TEST=none

Signed-off-by: Raul E Rangel 
Change-Id: Ibb18f363a215d665d53a722ed76896a75d1c5608
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42108
Reviewed-by: Aaron Durbin 
Reviewed-by: Furquan Shaikh 
Tested-by: build bot (Jenkins) 
---
M src/soc/amd/picasso/cpu.c
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Aaron Durbin: Looks good to me, approved
  Furquan Shaikh: Looks good to me, approved

diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c
index 3512c94..de9a2fa 100644
--- a/src/soc/amd/picasso/cpu.c
+++ b/src/soc/amd/picasso/cpu.c
@@ -98,7 +98,7 @@
    if (mp_init_with_smm(cpu_bus, &mp_ops) < 0)
    	printk(BIOS_ERR, "MP initialization failure.\n");

-	/* The flash is now no longer cacheable. Reset to WP for performance. */
+	/* pre_mp_init made the flash not cacheable. Reset to WP for performance. */
    mtrr_use_temp_range(FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT);

set_warm_reset_flag();

[9elements QA (Code Review)]

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42108 )

Change subject: soc/amd/picasso/cpu.c: Make comment clearer
......................................................................

Patch Set 2:

Automatic boot test returned (PASS/FAIL/TOTAL): 4/0/4
Emulation targets:
"QEMU x86 q35/ich9" using payload TianoCore : SUCCESS : https://lava.9esec.io/r/5215
"QEMU x86 q35/ich9" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/5214
"QEMU x86 i440fx/piix4" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/5213
"QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/5212

Please note: This test is under development and might not be accurate at all!