Hello Raul Rangel, Chris Wang,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/42216
to review the following change.
Change subject: soc/amd/picasso: Add UPD xhci0_force_gen1 ......................................................................
soc/amd/picasso: Add UPD xhci0_force_gen1
Add xhci0_force_gen1 UPD for force USB3 port to gen1
BUG=b:156314787 BRANCH=trembyle-bringup TEST=Build.
Cq-Depend: chrome-internal:3013435 Change-Id: Iff3746e248625c253776c3bc3946d123b0635ffe Signed-off-by: Chris Wang chris.wang@amd.corp-partner.google.com Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+... Reviewed-by: Raul E Rangel rrangel@chromium.org Reviewed-by: Furquan Shaikh furquan@chromium.org --- M src/soc/amd/picasso/chip.h M src/soc/amd/picasso/fsp_params.c 2 files changed, 9 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/42216/1
diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index e52751a..f5fbe0f 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -103,6 +103,8 @@ SD_EMMC_EMMC_HS400, SD_EMMC_EMMC_HS300, } sd_emmc_config; + + uint8_t xhci0_force_gen1; };
typedef struct soc_amd_picasso_config config_t; diff --git a/src/soc/amd/picasso/fsp_params.c b/src/soc/amd/picasso/fsp_params.c index 2d83220..e0620e5 100644 --- a/src/soc/amd/picasso/fsp_params.c +++ b/src/soc/amd/picasso/fsp_params.c @@ -95,6 +95,12 @@ fill_ddi_descriptors(scfg, fsp_ddi, num_ddi); }
+static void fsp_usb_oem_customization(FSP_S_CONFIG *scfg, + const struct soc_amd_picasso_config *cfg) +{ + scfg->xhci0_force_gen1 = cfg->xhci0_force_gen1; +} + void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) { const struct soc_amd_picasso_config *cfg; @@ -103,4 +109,5 @@ cfg = config_of_soc(); fsps_update_emmc_config(scfg, cfg); fsp_fill_pcie_ddi_descriptors(scfg); + fsp_usb_oem_customization(scfg, cfg); }
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42216 )
Change subject: soc/amd/picasso: Add UPD xhci0_force_gen1 ......................................................................
Patch Set 1:
(3 comments)
https://review.coreboot.org/c/coreboot/+/42216/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42216/1//COMMIT_MSG@9 PS1, Line 9: for to
https://review.coreboot.org/c/coreboot/+/42216/1//COMMIT_MSG@9 PS1, Line 9: Add xhci0_force_gen1 UPD for force USB3 port to gen1 Please add a dot/period at the end.
https://review.coreboot.org/c/coreboot/+/42216/1//COMMIT_MSG@10 PS1, Line 10: Please summarize the bug, I am denied access to.
What is the default, and why should gen1 ever be required? (I guess due to board design reasons?)
Hello build bot (Jenkins), Raul Rangel, Furquan Shaikh, Chris Wang,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42216
to look at the new patch set (#2).
Change subject: soc/amd/picasso: Add UPD xhci0_force_gen1 ......................................................................
soc/amd/picasso: Add UPD xhci0_force_gen1
Adding xhci0_force_gen1 UPD to force USB3 port to gen1.
BUG=b:156314787 BRANCH=trembyle-bringup TEST=Build.
Cq-Depend: chrome-internal:3013435 Change-Id: Iff3746e248625c253776c3bc3946d123b0635ffe Signed-off-by: Chris Wang chris.wang@amd.corp-partner.google.com Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+... Reviewed-by: Raul E Rangel rrangel@chromium.org Reviewed-by: Furquan Shaikh furquan@chromium.org --- M src/soc/amd/picasso/chip.h M src/soc/amd/picasso/fsp_params.c 2 files changed, 9 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/42216/2
chris wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42216 )
Change subject: soc/amd/picasso: Add UPD xhci0_force_gen1 ......................................................................
Patch Set 3:
(3 comments)
https://review.coreboot.org/c/coreboot/+/42216/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42216/1//COMMIT_MSG@9 PS1, Line 9: for
to
Done
https://review.coreboot.org/c/coreboot/+/42216/1//COMMIT_MSG@9 PS1, Line 9: Add xhci0_force_gen1 UPD for force USB3 port to gen1
Please add a dot/period at the end.
Done
https://review.coreboot.org/c/coreboot/+/42216/1//COMMIT_MSG@10 PS1, Line 10:
Please summarize the bug, I am denied access to. […]
this upd used for force the xhci to gen1. It depends on request. the default setting is disabled.
Eric Peers has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42216 )
Change subject: soc/amd/picasso: Add UPD xhci0_force_gen1 ......................................................................
Patch Set 3: Code-Review+1
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42216 )
Change subject: soc/amd/picasso: Add UPD xhci0_force_gen1 ......................................................................
Patch Set 3: Code-Review+2
Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42216 )
Change subject: soc/amd/picasso: Add UPD xhci0_force_gen1 ......................................................................
Patch Set 4: Code-Review+2
Chris Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42216 )
Change subject: soc/amd/picasso: Add UPD xhci0_force_gen1 ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42216/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42216/1//COMMIT_MSG@10 PS1, Line 10:
this upd used for force the xhci to gen1. It depends on request. […]
Done
Marshall Dawson has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42216 )
Change subject: soc/amd/picasso: Add UPD xhci0_force_gen1 ......................................................................
soc/amd/picasso: Add UPD xhci0_force_gen1
Adding xhci0_force_gen1 UPD to force USB3 port to gen1.
BUG=b:156314787 BRANCH=trembyle-bringup TEST=Build.
Cq-Depend: chrome-internal:3013435 Change-Id: Iff3746e248625c253776c3bc3946d123b0635ffe Signed-off-by: Chris Wang chris.wang@amd.corp-partner.google.com Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+... Reviewed-by: Raul E Rangel rrangel@chromium.org Reviewed-by: Furquan Shaikh furquan@chromium.org Reviewed-on: https://review.coreboot.org/c/coreboot/+/42216 Reviewed-by: Marshall Dawson marshalldawson3rd@gmail.com Reviewed-by: Eric Peers epeers@google.com Reviewed-by: Furquan Shaikh furquan@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/amd/picasso/chip.h M src/soc/amd/picasso/fsp_params.c 2 files changed, 9 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Marshall Dawson: Looks good to me, approved Eric Peers: Looks good to me, but someone else must approve
diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index e52751a..f5fbe0f 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -103,6 +103,8 @@ SD_EMMC_EMMC_HS400, SD_EMMC_EMMC_HS300, } sd_emmc_config; + + uint8_t xhci0_force_gen1; };
typedef struct soc_amd_picasso_config config_t; diff --git a/src/soc/amd/picasso/fsp_params.c b/src/soc/amd/picasso/fsp_params.c index 67fe7d8..9decbbf 100644 --- a/src/soc/amd/picasso/fsp_params.c +++ b/src/soc/amd/picasso/fsp_params.c @@ -95,6 +95,12 @@ fill_ddi_descriptors(scfg, fsp_ddi, num_ddi); }
+static void fsp_usb_oem_customization(FSP_S_CONFIG *scfg, + const struct soc_amd_picasso_config *cfg) +{ + scfg->xhci0_force_gen1 = cfg->xhci0_force_gen1; +} + void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) { const struct soc_amd_picasso_config *cfg; @@ -103,4 +109,5 @@ cfg = config_of_soc(); fsps_update_emmc_config(scfg, cfg); fsp_fill_pcie_ddi_descriptors(scfg); + fsp_usb_oem_customization(scfg, cfg); }