Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46782 )
Change subject: sb/intel/lynxpoint/acpi: Split USB into EHCI and xHCI ......................................................................
sb/intel/lynxpoint/acpi: Split USB into EHCI and xHCI
Tested with BUILD_TIMELESS=1, Google Wolf does not change.
Change-Id: I0ce8f1e4aaa86d2f7607fec9214dc64d1f530c88 Signed-off-by: Angel Pons th3fanbus@gmail.com --- A src/southbridge/intel/lynxpoint/acpi/ehci.asl M src/southbridge/intel/lynxpoint/acpi/pch.asl R src/southbridge/intel/lynxpoint/acpi/xhci.asl 3 files changed, 39 insertions(+), 35 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/46782/1
diff --git a/src/southbridge/intel/lynxpoint/acpi/ehci.asl b/src/southbridge/intel/lynxpoint/acpi/ehci.asl new file mode 100644 index 0000000..2a54304 --- /dev/null +++ b/src/southbridge/intel/lynxpoint/acpi/ehci.asl @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +// EHCI Controller 0:1d.0 + +Device (EHCI) +{ + Name (_ADR, 0x001d0000) + + Name (_PRW, Package () { DEFAULT_PRW_VALUE, 3 }) + + // Leave USB ports on for to allow Wake from USB + + Method (_S3D, 0) // Highest D State in S3 State + { + Return (2) + } + + Method (_S4D, 0) // Highest D State in S4 State + { + Return (2) + } + + Device (HUB7) + { + Name (_ADR, 0) + + Device (PRT1) { Name (_ADR, 1) } // USB Port 0 + Device (PRT2) { Name (_ADR, 2) } // USB Port 1 + Device (PRT3) { Name (_ADR, 3) } // USB Port 2 + Device (PRT4) { Name (_ADR, 4) } // USB Port 3 + Device (PRT5) { Name (_ADR, 5) } // USB Port 4 + Device (PRT6) { Name (_ADR, 6) } // USB Port 5 + } +} diff --git a/src/southbridge/intel/lynxpoint/acpi/pch.asl b/src/southbridge/intel/lynxpoint/acpi/pch.asl index e683c75..40d206d 100644 --- a/src/southbridge/intel/lynxpoint/acpi/pch.asl +++ b/src/southbridge/intel/lynxpoint/acpi/pch.asl @@ -67,8 +67,11 @@ // PCI Express Ports 0:1c.x #include <southbridge/intel/common/acpi/pcie.asl>
-// USB 0:1d.0 and 0:1a.0 -#include "usb.asl" +// USB EHCI 0:1d.0 and 0:1a.0 +#include "ehci.asl" + +// USB XHCI 0:14.0 +#include "xhci.asl"
// LPC Bridge 0:1f.0 #include "lpc.asl" diff --git a/src/southbridge/intel/lynxpoint/acpi/usb.asl b/src/southbridge/intel/lynxpoint/acpi/xhci.asl similarity index 91% rename from src/southbridge/intel/lynxpoint/acpi/usb.asl rename to src/southbridge/intel/lynxpoint/acpi/xhci.asl index fbb7090..65f1869 100644 --- a/src/southbridge/intel/lynxpoint/acpi/usb.asl +++ b/src/southbridge/intel/lynxpoint/acpi/xhci.asl @@ -1,38 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-// EHCI Controller 0:1d.0 - -Device (EHCI) -{ - Name (_ADR, 0x001d0000) - - Name (_PRW, Package () { DEFAULT_PRW_VALUE, 3 }) - - // Leave USB ports on for to allow Wake from USB - - Method (_S3D, 0) // Highest D State in S3 State - { - Return (2) - } - - Method (_S4D, 0) // Highest D State in S4 State - { - Return (2) - } - - Device (HUB7) - { - Name (_ADR, 0) - - Device (PRT1) { Name (_ADR, 1) } // USB Port 0 - Device (PRT2) { Name (_ADR, 2) } // USB Port 1 - Device (PRT3) { Name (_ADR, 3) } // USB Port 2 - Device (PRT4) { Name (_ADR, 4) } // USB Port 3 - Device (PRT5) { Name (_ADR, 5) } // USB Port 4 - Device (PRT6) { Name (_ADR, 6) } // USB Port 5 - } -} - // XHCI Controller 0:14.0
Device (XHCI)
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46782 )
Change subject: sb/intel/lynxpoint/acpi: Split USB into EHCI and xHCI ......................................................................
Patch Set 8: Code-Review+2
Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46782 )
Change subject: sb/intel/lynxpoint/acpi: Split USB into EHCI and xHCI ......................................................................
sb/intel/lynxpoint/acpi: Split USB into EHCI and xHCI
Tested with BUILD_TIMELESS=1, Google Wolf does not change.
Change-Id: I0ce8f1e4aaa86d2f7607fec9214dc64d1f530c88 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/46782 Reviewed-by: Michael Niewöhner foss@mniewoehner.de Tested-by: build bot (Jenkins) no-reply@coreboot.org --- A src/southbridge/intel/lynxpoint/acpi/ehci.asl M src/southbridge/intel/lynxpoint/acpi/pch.asl R src/southbridge/intel/lynxpoint/acpi/xhci.asl 3 files changed, 39 insertions(+), 35 deletions(-)
Approvals: build bot (Jenkins): Verified Michael Niewöhner: Looks good to me, approved
diff --git a/src/southbridge/intel/lynxpoint/acpi/ehci.asl b/src/southbridge/intel/lynxpoint/acpi/ehci.asl new file mode 100644 index 0000000..2a54304 --- /dev/null +++ b/src/southbridge/intel/lynxpoint/acpi/ehci.asl @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +// EHCI Controller 0:1d.0 + +Device (EHCI) +{ + Name (_ADR, 0x001d0000) + + Name (_PRW, Package () { DEFAULT_PRW_VALUE, 3 }) + + // Leave USB ports on for to allow Wake from USB + + Method (_S3D, 0) // Highest D State in S3 State + { + Return (2) + } + + Method (_S4D, 0) // Highest D State in S4 State + { + Return (2) + } + + Device (HUB7) + { + Name (_ADR, 0) + + Device (PRT1) { Name (_ADR, 1) } // USB Port 0 + Device (PRT2) { Name (_ADR, 2) } // USB Port 1 + Device (PRT3) { Name (_ADR, 3) } // USB Port 2 + Device (PRT4) { Name (_ADR, 4) } // USB Port 3 + Device (PRT5) { Name (_ADR, 5) } // USB Port 4 + Device (PRT6) { Name (_ADR, 6) } // USB Port 5 + } +} diff --git a/src/southbridge/intel/lynxpoint/acpi/pch.asl b/src/southbridge/intel/lynxpoint/acpi/pch.asl index e683c75..40d206d 100644 --- a/src/southbridge/intel/lynxpoint/acpi/pch.asl +++ b/src/southbridge/intel/lynxpoint/acpi/pch.asl @@ -67,8 +67,11 @@ // PCI Express Ports 0:1c.x #include <southbridge/intel/common/acpi/pcie.asl>
-// USB 0:1d.0 and 0:1a.0 -#include "usb.asl" +// USB EHCI 0:1d.0 and 0:1a.0 +#include "ehci.asl" + +// USB XHCI 0:14.0 +#include "xhci.asl"
// LPC Bridge 0:1f.0 #include "lpc.asl" diff --git a/src/southbridge/intel/lynxpoint/acpi/usb.asl b/src/southbridge/intel/lynxpoint/acpi/xhci.asl similarity index 91% rename from src/southbridge/intel/lynxpoint/acpi/usb.asl rename to src/southbridge/intel/lynxpoint/acpi/xhci.asl index fbb7090..65f1869 100644 --- a/src/southbridge/intel/lynxpoint/acpi/usb.asl +++ b/src/southbridge/intel/lynxpoint/acpi/xhci.asl @@ -1,38 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-// EHCI Controller 0:1d.0 - -Device (EHCI) -{ - Name (_ADR, 0x001d0000) - - Name (_PRW, Package () { DEFAULT_PRW_VALUE, 3 }) - - // Leave USB ports on for to allow Wake from USB - - Method (_S3D, 0) // Highest D State in S3 State - { - Return (2) - } - - Method (_S4D, 0) // Highest D State in S4 State - { - Return (2) - } - - Device (HUB7) - { - Name (_ADR, 0) - - Device (PRT1) { Name (_ADR, 1) } // USB Port 0 - Device (PRT2) { Name (_ADR, 2) } // USB Port 1 - Device (PRT3) { Name (_ADR, 3) } // USB Port 2 - Device (PRT4) { Name (_ADR, 4) } // USB Port 3 - Device (PRT5) { Name (_ADR, 5) } // USB Port 4 - Device (PRT6) { Name (_ADR, 6) } // USB Port 5 - } -} - // XHCI Controller 0:14.0
Device (XHCI)
-
Angel Pons (Code Review) -
Michael Niewöhner (Code Review)