Jamie Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38425 )
Change subject: mainboard/google/puff: update USB configuration ......................................................................
mainboard/google/puff: update USB configuration
Base on USB SI report to fine tune the strength and correct some OC pin settings.
BRANCH=none BUG=b:147206010 TEST=build and test all usb ports function work fine.
Change-Id: Idbee5cdddf3a83f97109214a95e0f9875b3b3f8f Signed-off-by: Jamie Chen jamie.chen@intel.com --- M src/mainboard/google/hatch/variants/puff/overridetree.cb 1 file changed, 92 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/38425/1
diff --git a/src/mainboard/google/hatch/variants/puff/overridetree.cb b/src/mainboard/google/hatch/variants/puff/overridetree.cb index e3ccc61..402b98b 100644 --- a/src/mainboard/google/hatch/variants/puff/overridetree.cb +++ b/src/mainboard/google/hatch/variants/puff/overridetree.cb @@ -15,10 +15,59 @@ [PchSerialIoIndexUART2] = PchSerialIoDisabled, }"
- # USB configuration - register "usb2_ports[4]" = "USB2_PORT_SHORT(OC_SKIP)" + # USB configuration + register "usb2_ports[0]" = "USB2_PORT_MID(OC2)" # Type-A Port 2 + register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port + register "usb2_ports[2]" = "{ + .enable = 1, + .ocpin = OC3, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port 3 + register "usb2_ports[3]" = "{ + .enable = 1, + .ocpin = OC1, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port 1 + register "usb2_ports[4]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port 4 + register "usb2_ports[5]" = "{ + .enable = 1, + .ocpin = OC0, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A port 0 register "usb2_ports[6]" = "USB2_PORT_EMPTY" - register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb2_ports[7]" = "USB2_PORT_EMPTY" + register "usb2_ports[8]" = "USB2_PORT_EMPTY" + register "usb2_ports[9]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # BT + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port 2 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port 3 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port 1 + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port 0 + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port 4
# Enable eMMC HS400 register "ScsEmmcHs400Enabled" = "1" @@ -127,6 +176,26 @@ chip drivers/usb/acpi device usb 0.0 on chip drivers/usb/acpi + register "desc" = ""Type-A Port 2"" + register "type" = "UPC_TYPE_A" + device usb 2.0 on end + end + chip drivers/usb/acpi + register "desc" = ""Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device usb 2.1 on end + end + chip drivers/usb/acpi + register "desc" = ""Type-A Port 3"" + register "type" = "UPC_TYPE_A" + device usb 2.2 on end + end + chip drivers/usb/acpi + register "desc" = ""Type-A Port 1"" + register "type" = "UPC_TYPE_A" + device usb 2.3 on end + end + chip drivers/usb/acpi register "desc" = ""Type-A Port 4"" register "type" = "UPC_TYPE_A" device usb 2.4 on end @@ -140,6 +209,26 @@ device usb 2.6 off end end chip drivers/usb/acpi + register "desc" = ""Type-A Port 2"" + register "type" = "UPC_TYPE_USB3_A" + device usb 3.0 on end + end + chip drivers/usb/acpi + register "desc" = ""Type-A Port 3"" + register "type" = "UPC_TYPE_USB3_A" + device usb 3.1 on end + end + chip drivers/usb/acpi + register "desc" = ""Type-A Port 1"" + register "type" = "UPC_TYPE_USB3_A" + device usb 3.2 on end + end + chip drivers/usb/acpi + register "desc" = ""Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device usb 3.3 on end + end + chip drivers/usb/acpi register "desc" = ""Type-A Port 0"" register "type" = "UPC_TYPE_USB3_A" device usb 3.4 on end
Kangheui Won has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38425 )
Change subject: mainboard/google/puff: update USB configuration ......................................................................
Patch Set 1: Code-Review+1
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38425 )
Change subject: mainboard/google/puff: update USB configuration ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38425/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38425/1//COMMIT_MSG@9 PS1, Line 9: USB SI report What dose SI stand for?
Kane Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38425 )
Change subject: mainboard/google/puff: update USB configuration ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38425/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38425/1//COMMIT_MSG@9 PS1, Line 9: USB SI report
What dose SI stand for?
signal integrity.
Kane Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38425 )
Change subject: mainboard/google/puff: update USB configuration ......................................................................
Patch Set 1: Code-Review+1
Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38425 )
Change subject: mainboard/google/puff: update USB configuration ......................................................................
Patch Set 1: Code-Review+2
Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38425 )
Change subject: mainboard/google/puff: update USB configuration ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38425/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38425/1//COMMIT_MSG@9 PS1, Line 9: USB SI report
signal integrity.
.
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38425 )
Change subject: mainboard/google/puff: update USB configuration ......................................................................
mainboard/google/puff: update USB configuration
Base on USB SI report to fine tune the strength and correct some OC pin settings.
BRANCH=none BUG=b:147206010 TEST=build and test all usb ports function work fine.
Change-Id: Idbee5cdddf3a83f97109214a95e0f9875b3b3f8f Signed-off-by: Jamie Chen jamie.chen@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/38425 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Kangheui Won khwon@chromium.org Reviewed-by: Kane Chen kane.chen@intel.corp-partner.google.com Reviewed-by: Edward O'Callaghan quasisec@chromium.org --- M src/mainboard/google/hatch/variants/puff/overridetree.cb 1 file changed, 92 insertions(+), 3 deletions(-)
Approvals: build bot (Jenkins): Verified Edward O'Callaghan: Looks good to me, approved Kane Chen: Looks good to me, but someone else must approve Kangheui Won: Looks good to me, but someone else must approve
diff --git a/src/mainboard/google/hatch/variants/puff/overridetree.cb b/src/mainboard/google/hatch/variants/puff/overridetree.cb index e3ccc61..402b98b 100644 --- a/src/mainboard/google/hatch/variants/puff/overridetree.cb +++ b/src/mainboard/google/hatch/variants/puff/overridetree.cb @@ -15,10 +15,59 @@ [PchSerialIoIndexUART2] = PchSerialIoDisabled, }"
- # USB configuration - register "usb2_ports[4]" = "USB2_PORT_SHORT(OC_SKIP)" + # USB configuration + register "usb2_ports[0]" = "USB2_PORT_MID(OC2)" # Type-A Port 2 + register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port + register "usb2_ports[2]" = "{ + .enable = 1, + .ocpin = OC3, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port 3 + register "usb2_ports[3]" = "{ + .enable = 1, + .ocpin = OC1, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port 1 + register "usb2_ports[4]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port 4 + register "usb2_ports[5]" = "{ + .enable = 1, + .ocpin = OC0, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A port 0 register "usb2_ports[6]" = "USB2_PORT_EMPTY" - register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb2_ports[7]" = "USB2_PORT_EMPTY" + register "usb2_ports[8]" = "USB2_PORT_EMPTY" + register "usb2_ports[9]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # BT + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port 2 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port 3 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port 1 + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port 0 + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port 4
# Enable eMMC HS400 register "ScsEmmcHs400Enabled" = "1" @@ -127,6 +176,26 @@ chip drivers/usb/acpi device usb 0.0 on chip drivers/usb/acpi + register "desc" = ""Type-A Port 2"" + register "type" = "UPC_TYPE_A" + device usb 2.0 on end + end + chip drivers/usb/acpi + register "desc" = ""Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device usb 2.1 on end + end + chip drivers/usb/acpi + register "desc" = ""Type-A Port 3"" + register "type" = "UPC_TYPE_A" + device usb 2.2 on end + end + chip drivers/usb/acpi + register "desc" = ""Type-A Port 1"" + register "type" = "UPC_TYPE_A" + device usb 2.3 on end + end + chip drivers/usb/acpi register "desc" = ""Type-A Port 4"" register "type" = "UPC_TYPE_A" device usb 2.4 on end @@ -140,6 +209,26 @@ device usb 2.6 off end end chip drivers/usb/acpi + register "desc" = ""Type-A Port 2"" + register "type" = "UPC_TYPE_USB3_A" + device usb 3.0 on end + end + chip drivers/usb/acpi + register "desc" = ""Type-A Port 3"" + register "type" = "UPC_TYPE_USB3_A" + device usb 3.1 on end + end + chip drivers/usb/acpi + register "desc" = ""Type-A Port 1"" + register "type" = "UPC_TYPE_USB3_A" + device usb 3.2 on end + end + chip drivers/usb/acpi + register "desc" = ""Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device usb 3.3 on end + end + chip drivers/usb/acpi register "desc" = ""Type-A Port 0"" register "type" = "UPC_TYPE_USB3_A" device usb 3.4 on end
-
Edward O'Callaghan (Code Review) -
Jamie Chen (Code Review)
-
Kane Chen (Code Review)
-
Kangheui Won (Code Review)
-
Patrick Georgi (Code Review)
-
Paul Menzel (Code Review)