[L] Change in coreboot[main]: mainboard/intel/frost_creek: Add a new CRB Frost Creek for Snow Ridge

[Name of user not set (Code Review)]

Attention is currently required from: Elyes Haouas, Felix Singer, Jérémy Compostella, Shuo Liu, Vasiliy Khoruzhick.

[e-mail] has posted comments on this change by [e-mail]. ( https://review.coreboot.org/c/coreboot/+/83322?usp=email )

Change subject: mainboard/intel/frost_creek: Add a new CRB Frost Creek for Snow Ridge
......................................................................

Patch Set 30:

(4 comments)

File src/mainboard/intel/frost_creek/board.fmd:

https://review.coreboot.org/c/coreboot/+/83322/comment/9b716560_db583bde?usp... :
PS19, Line 7: 		COREBOOT(CBFS)@0x51200 0x00baee00
> bases could be omitted here if no explicit alignment reqs.

Done

File src/mainboard/intel/frost_creek/gpio.inc:

https://review.coreboot.org/c/coreboot/+/83322/comment/74ed9939_cf4c0d9d?usp... :
PS19, Line 112: 	SNR_PAD_CFG_STRUCT0(
> update the alignments?

This is automatically formatted by .clang-format, but it still looks a little bit strange.

File src/mainboard/intel/frost_creek/romstage.c:

https://review.coreboot.org/c/coreboot/+/83322/comment/58aa2ab8_e8a27f26?usp... :
PS19, Line 20: 	uint32_t boardid = board_id();
> do we still need board_id here?

On some other board the board ID may be read from GPIO, but on Frost Creek, it's hardcoded.

https://review.coreboot.org/c/coreboot/+/83322/comment/35519c89_295b2188?usp... :
PS19, Line 51: 	for (lane = 0; lane < BL_MAX_FIA_LANES; lane++) {
> can you comment here?

HSIO lanes can be configured to map to PCH PCIe root ports, SATA ports and USB port. For this CRB, we just leave it as default.