[S] Change in coreboot[main]: soc/intel/common/block/cpu: Add Kconfig for effective way size for NEM+

[Subrata Banik (Code Review)]

Attention is currently required from: Ashish Kumar Mishra, Jérémy Compostella, Paul Menzel, Sowmya Aralguppe, Wonkyu Kim.

Subrata Banik has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/83946?usp=email )

The change is no longer submittable: All-Comments-Resolved is unsatisfied now.

Change subject: soc/intel/common/block/cpu: Add Kconfig for effective way size for NEM+
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Patch Set 13:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/83946/comment/960dc1b8_91fd5db6?usp... :
PS13, Line 23: The issue addressed by this commit can be observed with the following
             : experiment: using a 18 MB LLC SKU, set `DCACHE_RAM_SIZE` to
             : 0x400000 (4 MB).
This isn't a real issue, it's just a hypothesis that CONFIG_DCACHE_RAM_SIZE is larger than the way size.

I've never seen a platform and SoC combination like this before, and I'm worried about adding more hypothetical code to the bootblock, which is technically read-only for us. If there's a problem with a field device later, we won't be able to fix it.

If you see this hypothesis is true for the PTL platform (without tweaking the code like you did to replicate the issue), then we need to figure out why it's only happening on the PTL. We haven't seen this combination on other eNEM-based solutions in a long time.

Also, please only apply the solution to the PTL platform if necessary (and only after you answer my question above). We shouldn't be touching the bootblock of a shipped device unless we have to. We can test the PTL to see if this code is really necessary.