Change in coreboot[master]: soc/mediatek: PCI: Assert PERST# at bootblock stage

[Hung-Te Lin (Code Review)]

Attention is currently required from: Shelley Chen, Rex-BC Chen, Paul Menzel, Angel Pons, Yu-Ping Wu, Jianjun Wang.
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62359 )

Change subject: soc/mediatek: PCI: Assert PERST# at bootblock stage
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Patch Set 17:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/62359/comment/56b5ab30_77ed2028 
PS9, Line 14: 100ms
> we just need to use 8 bytes to store this information (uint64_t)

I tend to agree with the proposal - create something like WATCHDOG_TOMBSTONE in SRAM and simply use it as a timestamp for pre-init, since it's within coreboot stages (not some info that will be read by depthcharge) and also much easier to implement and maintain.