Change in coreboot[master]: soc/intel/{adl, common}: Add routines into CSE IA-common code

[Subrata Banik (Code Review)]

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph.
Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61518 )

Change subject: soc/intel/{adl, common}: Add routines into CSE IA-common code
......................................................................

soc/intel/{adl, common}: Add routines into CSE IA-common code

This patch adds routines to keep CSE and other HECI devices into the
lower power device state (AKA D0I3).
- cse_set_to_d0i3       =>  Set CSE device state to D0I3
- soc_set_d0i3_for_heci =>  SoC callback to set D0I3 for all HECI
                            devices

Additionally, Alder Lake implements SoC override to set D0I3 for all
HECI devices.

BUG=b:211954778
TEST=Able to build and boot Brya.

Signed-off-by: Subrata Banik 
Change-Id: Ie32887196628fe6386896604e50338f4bc0bedfe
---
M src/soc/intel/alderlake/finalize.c
M src/soc/intel/common/block/cse/cse.c
M src/soc/intel/common/block/include/intelblocks/cse.h
3 files changed, 23 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/61518/1

diff --git a/src/soc/intel/alderlake/finalize.c b/src/soc/intel/alderlake/finalize.c
index 589ea59..fc4c51a 100644
--- a/src/soc/intel/alderlake/finalize.c
+++ b/src/soc/intel/alderlake/finalize.c
@@ -80,7 +80,8 @@
    	sa_lock_pam();
 }

-static void heci_finalize(void)
+/* Function to set D0I3 for all HECI devices */
+void soc_set_d0i3_for_heci(void)
 {
    unsigned int cse_dev[] = {
    	PCH_DEVFN_CSE,
@@ -105,7 +106,7 @@
    apm_control(APM_CNT_FINALIZE);
    tbt_finalize();
    sa_finalize();
-	heci_finalize();
+	soc_set_d0i3_for_heci();

/* Indicate finalize step with post code */
    post_code(POST_OS_BOOT);
diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c
index 32f6d4f..dd9c7c1 100644
--- a/src/soc/intel/common/block/cse/cse.c
+++ b/src/soc/intel/common/block/cse/cse.c
@@ -69,6 +69,12 @@
 #define MEI_HDR_CSE_ADDR_START	0
 #define MEI_HDR_CSE_ADDR	(((1 << 8) - 1) << MEI_HDR_CSE_ADDR_START)

+/* SoC override function */
+__weak void soc_set_d0i3_for_heci(void)
+{
+	/* no-op */
+}
+
 /* Get HECI BAR 0 from PCI configuration space */
 static uintptr_t get_cse_bar(pci_devfn_t dev)
 {
@@ -988,6 +994,14 @@
    return true;
 }

+void cse_set_to_d0i3(void)
+{
+	if (!is_cse_devfn_visible(PCH_DEVFN_CSE))
+		return;
+
+	set_cse_device_state(PCH_DEVFN_CSE, DEV_IDLE);
+}
+
 #if ENV_RAMSTAGE

/*
diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h
index 15b7313..3d99b5c 100644
--- a/src/soc/intel/common/block/include/intelblocks/cse.h
+++ b/src/soc/intel/common/block/include/intelblocks/cse.h
@@ -489,6 +489,9 @@
 /* Function to make cse disable using PMC IPC */
 bool cse_disable_mei_devices(void);

+/* Set CSE device state to D0I3 */
+void cse_set_to_d0i3(void);
+
 /*
  * SoC override API to make heci1 disable using PCR.
  *
@@ -497,4 +500,7 @@
  */
 void soc_disable_heci1_using_pcr(void);

+/* SoC callback to set D0I3 for all HECI devices */
+void soc_set_d0i3_for_heci(void);
+
 #endif // SOC_INTEL_COMMON_CSE_H