Dan Elkouby has posted comments on this change. ( https://review.coreboot.org/25664 )
Change subject: nb/intel/sandybridge: support more XMP timings ......................................................................
Patch Set 1:
(3 comments)
https://review.coreboot.org/#/c/25664/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/25664/1//COMMIT_MSG@8 PS1, Line 8:
How did you test it ? […]
Forgot to write up a more detailed commit message. On it.
https://review.coreboot.org/#/c/25664/1/src/northbridge/intel/sandybridge/ra... File src/northbridge/intel/sandybridge/raminit_common.c:
https://review.coreboot.org/#/c/25664/1/src/northbridge/intel/sandybridge/ra... PS1, Line 2362: cmdrate = MIN(DIV_ROUND_UP(ctrl->tCMD, ctrl->tCK) - 1, 1);
As long as you can't prove that it'll work on any board (see comment above): No. […]
The value here is offset by 1: 0 for a CMD rate of 1, 1 for a CMD rate of 2. The point of the MIN() is to make sure cmdrate < 2.
https://review.coreboot.org/#/c/25664/1/src/northbridge/intel/sandybridge/ra... File src/northbridge/intel/sandybridge/raminit_ivy.c:
https://review.coreboot.org/#/c/25664/1/src/northbridge/intel/sandybridge/ra... PS1, Line 485: ctrl->CWL = get_CWL(ctrl->tCK);
why not […]
In my case, the XMP timing is tighter than the hardcoded LUT, this matches what the vendor firmware I compared against does.