[S] Change in coreboot[master]: soc/amd/mendocino: Add FSP parameter for eDP power sequence adjustment

[Chris Wang (Code Review)]

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held.

Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/74758

to look at the new patch set (#2).

Change subject: soc/amd/mendocino: Add FSP parameter for eDP power sequence adjustment
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soc/amd/mendocino: Add FSP parameter for eDP power sequence adjustment

Add UPD parameter for eDP power sequence adjust.

The pwr_down_bloff_to_varybloff is set one unit per 4ms.

BUG=b:271704149
TEST=Build; Verify the UPD was pass to system integrated table.

Signed-off-by: Chris Wang 
Change-Id: Ibdf50db12d982b45edca205e8f4612deb702453d
---
M src/soc/amd/mendocino/chip.h
M src/soc/amd/mendocino/fsp_m_params.c
2 files changed, 21 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/74758/2