Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46945 )
Change subject: mb/google/auron: Use Haswell CPU code ......................................................................
mb/google/auron: Use Haswell CPU code
The VR config and S0ix options are now specified for the CPU chip.
Change-Id: I75e405d41b4a0605e786fe761c92535e62d0cfce Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/google/auron/Kconfig M src/mainboard/google/auron/devicetree.cb M src/mainboard/google/auron/variants/buddy/overridetree.cb M src/mainboard/google/auron/variants/samus/overridetree.cb 4 files changed, 28 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/46945/1
diff --git a/src/mainboard/google/auron/Kconfig b/src/mainboard/google/auron/Kconfig index 8e49255..9c705e1 100644 --- a/src/mainboard/google/auron/Kconfig +++ b/src/mainboard/google/auron/Kconfig @@ -1,6 +1,7 @@
config BOARD_GOOGLE_BASEBOARD_AURON def_bool n + select CPU_INTEL_HASWELL select SOC_INTEL_BROADWELL select BOARD_ROMSIZE_KB_8192 select EC_GOOGLE_CHROMEEC diff --git a/src/mainboard/google/auron/devicetree.cb b/src/mainboard/google/auron/devicetree.cb index 26a5336..6aa9582 100644 --- a/src/mainboard/google/auron/devicetree.cb +++ b/src/mainboard/google/auron/devicetree.cb @@ -15,10 +15,13 @@ # Set backlight PWM value for eDP register "gpu_pch_backlight_pwm_hz" = "200"
- register "s0ix_enable" = "1" - device cpu_cluster 0 on - device lapic 0 on end + chip cpu/intel/haswell + register "s0ix_enable" = "1" + + device lapic 0 on end + device lapic 0xacac off end + end end
device domain 0 on diff --git a/src/mainboard/google/auron/variants/buddy/overridetree.cb b/src/mainboard/google/auron/variants/buddy/overridetree.cb index 60fb08c..1fd9e86 100644 --- a/src/mainboard/google/auron/variants/buddy/overridetree.cb +++ b/src/mainboard/google/auron/variants/buddy/overridetree.cb @@ -7,7 +7,14 @@ register "gpu_panel_power_backlight_on_delay" = "70" # 7ms register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms
- register "s0ix_enable" = "0" + device cpu_cluster 0 on + chip cpu/intel/haswell + register "s0ix_enable" = "0" + + device lapic 0 on end + device lapic 0xacac off end + end + end
device domain 0 on chip soc/intel/broadwell/pch diff --git a/src/mainboard/google/auron/variants/samus/overridetree.cb b/src/mainboard/google/auron/variants/samus/overridetree.cb index d8aec0a..d7bc611 100644 --- a/src/mainboard/google/auron/variants/samus/overridetree.cb +++ b/src/mainboard/google/auron/variants/samus/overridetree.cb @@ -10,11 +10,20 @@ register "gpu_panel_power_backlight_on_delay" = "2000" # 200ms register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms
- register "vr_slow_ramp_rate_set" = "3" - register "vr_slow_ramp_rate_enable" = "1" + device cpu_cluster 0 on + chip cpu/intel/haswell + # Disable S0ix for now + register "s0ix_enable" = "0"
- # Disable S0ix for now - register "s0ix_enable" = "0" + register "vr_config" = "{ + .slow_ramp_rate_set = 3, + .slow_ramp_rate_enable = true, + }" + + device lapic 0 on end + device lapic 0xacac off end + end + end
device domain 0 on chip soc/intel/broadwell/pch
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46945
to look at the new patch set (#5).
Change subject: mb/google/auron: Use Haswell CPU code ......................................................................
mb/google/auron: Use Haswell CPU code
The VR config and S0ix options are now specified for the CPU chip.
Change-Id: I75e405d41b4a0605e786fe761c92535e62d0cfce Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/google/auron/Kconfig M src/mainboard/google/auron/devicetree.cb M src/mainboard/google/auron/variants/buddy/overridetree.cb M src/mainboard/google/auron/variants/samus/overridetree.cb 4 files changed, 28 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/46945/5
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46945
to look at the new patch set (#11).
Change subject: mb/google/auron: Use Haswell CPU code ......................................................................
mb/google/auron: Use Haswell CPU code
The VR config and S0ix options are now specified for the CPU chip.
Change-Id: I75e405d41b4a0605e786fe761c92535e62d0cfce Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/google/auron/Kconfig M src/mainboard/google/auron/devicetree.cb M src/mainboard/google/auron/variants/buddy/overridetree.cb M src/mainboard/google/auron/variants/samus/overridetree.cb 4 files changed, 28 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/46945/11
Attention is currently required from: Angel Pons. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46945 )
Change subject: mb/google/auron: Use Haswell CPU code ......................................................................
Patch Set 15: Code-Review+2
Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46945 )
Change subject: mb/google/auron: Use Haswell CPU code ......................................................................
mb/google/auron: Use Haswell CPU code
The VR config and S0ix options are now specified for the CPU chip.
Change-Id: I75e405d41b4a0605e786fe761c92535e62d0cfce Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/46945 Reviewed-by: Arthur Heymans arthur@aheymans.xyz Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/auron/Kconfig M src/mainboard/google/auron/devicetree.cb M src/mainboard/google/auron/variants/buddy/overridetree.cb M src/mainboard/google/auron/variants/samus/overridetree.cb 4 files changed, 28 insertions(+), 8 deletions(-)
Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved
diff --git a/src/mainboard/google/auron/Kconfig b/src/mainboard/google/auron/Kconfig index 5301e32..293a973 100644 --- a/src/mainboard/google/auron/Kconfig +++ b/src/mainboard/google/auron/Kconfig @@ -1,6 +1,7 @@
config BOARD_GOOGLE_BASEBOARD_AURON def_bool n + select CPU_INTEL_HASWELL select SOC_INTEL_BROADWELL select BOARD_ROMSIZE_KB_8192 select EC_GOOGLE_CHROMEEC diff --git a/src/mainboard/google/auron/devicetree.cb b/src/mainboard/google/auron/devicetree.cb index 8bf2c12..39c6554 100644 --- a/src/mainboard/google/auron/devicetree.cb +++ b/src/mainboard/google/auron/devicetree.cb @@ -12,10 +12,13 @@ # Enable HDMI Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06"
- register "s0ix_enable" = "1" - device cpu_cluster 0 on - device lapic 0 on end + chip cpu/intel/haswell + register "s0ix_enable" = "1" + + device lapic 0 on end + device lapic 0xacac off end + end end
device domain 0 on diff --git a/src/mainboard/google/auron/variants/buddy/overridetree.cb b/src/mainboard/google/auron/variants/buddy/overridetree.cb index 6762eb4..0570cdc 100644 --- a/src/mainboard/google/auron/variants/buddy/overridetree.cb +++ b/src/mainboard/google/auron/variants/buddy/overridetree.cb @@ -9,7 +9,14 @@ .backlight_pwm_hz = 200, }"
- register "s0ix_enable" = "0" + device cpu_cluster 0 on + chip cpu/intel/haswell + register "s0ix_enable" = "0" + + device lapic 0 on end + device lapic 0xacac off end + end + end
device domain 0 on chip soc/intel/broadwell/pch diff --git a/src/mainboard/google/auron/variants/samus/overridetree.cb b/src/mainboard/google/auron/variants/samus/overridetree.cb index 34a785b..0a92efe 100644 --- a/src/mainboard/google/auron/variants/samus/overridetree.cb +++ b/src/mainboard/google/auron/variants/samus/overridetree.cb @@ -12,11 +12,20 @@ .backlight_pwm_hz = 200, }"
- register "vr_slow_ramp_rate_set" = "3" - register "vr_slow_ramp_rate_enable" = "1" + device cpu_cluster 0 on + chip cpu/intel/haswell + # Disable S0ix for now + register "s0ix_enable" = "0"
- # Disable S0ix for now - register "s0ix_enable" = "0" + register "vr_config" = "{ + .slow_ramp_rate_set = 3, + .slow_ramp_rate_enable = true, + }" + + device lapic 0 on end + device lapic 0xacac off end + end + end
device domain 0 on chip soc/intel/broadwell/pch
-
Angel Pons (Code Review) -
Arthur Heymans (Code Review)