Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57043 )
Change subject: soc/mediatek/mt8195: Update clock square setting ......................................................................
soc/mediatek/mt8195: Update clock square setting
To reduce suspend power consumption, 1. Disable unused CLKSQ2. 2. Set CLKSQ_EN to sleep control for SPM 26M sleep control. No bus clock when enter 26m sleep control, and only control clock square by side band.
Signed-off-by: Chun-Jie Chen chun-jie.chen@mediatek.com Change-Id: Ia9a1735d6f508ce35b9af2d67831a3474255198b Reviewed-on: https://review.coreboot.org/c/coreboot/+/57043 Reviewed-by: Yu-Ping Wu yupingso@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/mediatek/mt8195/pll.c 1 file changed, 8 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved
diff --git a/src/soc/mediatek/mt8195/pll.c b/src/soc/mediatek/mt8195/pll.c index ebdc37f..74dd150 100644 --- a/src/soc/mediatek/mt8195/pll.c +++ b/src/soc/mediatek/mt8195/pll.c @@ -638,12 +638,18 @@ int i;
/* enable clock square */ - setbits32(&mtk_apmixed->ap_pll_con0, 0x4); + setbits32(&mtk_apmixed->ap_pll_con0, BIT(2));
udelay(PLL_CKSQ_ON_DELAY);
/* enable clock square1 low-pass filter */ - setbits32(&mtk_apmixed->ap_pll_con0, 0x2); + setbits32(&mtk_apmixed->ap_pll_con0, BIT(1)); + + /* + * BIT(3): 1 for register control; 0 for sleep control + * BIT(8): 1 to enable clock square2; 0 to disable it + */ + clrbits32(&mtk_apmixed->ap_pll_con0, BIT(3) | BIT(8));
/* xPLL PWR ON */ for (i = 0; i < APMIXED_PLL_MAX; i++)