Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35751 )
Change subject: soc/intel/braswell/chip.h: Add IGD_MEMSIZE_xxMB ......................................................................
soc/intel/braswell/chip.h: Add IGD_MEMSIZE_xxMB
Add defines to have some more readable code for devcietree.cb.
BUG=N/A TEST=4K HDMI monitor and LCD working fine on Facebook FBG-1701
Change-Id: Ifc1a7657a528d1fc570dd16df66b078e37e014cb Signed-off-by: Frans Hendriks fhendriks@eltan.com --- M src/soc/intel/braswell/chip.h 1 file changed, 5 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/35751/1
diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h index 747b941..9f790dc 100644 --- a/src/soc/intel/braswell/chip.h +++ b/src/soc/intel/braswell/chip.h @@ -32,6 +32,11 @@ #define SVID_CONFIG3 3 #define SVID_PMIC_CONFIG 8
+#define IGD_MEMSIZE_32MB 0x01 +#define IGD_MEMSIZE_64MB 0x02 +#define IGD_MEMSIZE_96MB 0x03 +#define IGD_MEMSIZE_128MB 0x04 + enum lpe_clk_src { LPE_CLK_SRC_XTAL, LPE_CLK_SRC_PLL,
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35751 )
Change subject: soc/intel/braswell/chip.h: Add IGD_MEMSIZE_xxMB ......................................................................
Patch Set 1: Code-Review+2
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35751 )
Change subject: soc/intel/braswell/chip.h: Add IGD_MEMSIZE_xxMB ......................................................................
Patch Set 1:
Add that to all Intel SoCs?
Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35751 )
Change subject: soc/intel/braswell/chip.h: Add IGD_MEMSIZE_xxMB ......................................................................
Patch Set 1:
Patch Set 1:
Add that to all Intel SoCs?
Not sure if other SoC have this (FSP) parameter also.
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/35751 )
Change subject: soc/intel/braswell/chip.h: Add IGD_MEMSIZE_xxMB ......................................................................
soc/intel/braswell/chip.h: Add IGD_MEMSIZE_xxMB
Add defines to have some more readable code for devcietree.cb.
BUG=N/A TEST=4K HDMI monitor and LCD working fine on Facebook FBG-1701
Change-Id: Ifc1a7657a528d1fc570dd16df66b078e37e014cb Signed-off-by: Frans Hendriks fhendriks@eltan.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/35751 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Patrick Rudolph siro@das-labor.org --- M src/soc/intel/braswell/chip.h 1 file changed, 5 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved
diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h index 747b941..9f790dc 100644 --- a/src/soc/intel/braswell/chip.h +++ b/src/soc/intel/braswell/chip.h @@ -32,6 +32,11 @@ #define SVID_CONFIG3 3 #define SVID_PMIC_CONFIG 8
+#define IGD_MEMSIZE_32MB 0x01 +#define IGD_MEMSIZE_64MB 0x02 +#define IGD_MEMSIZE_96MB 0x03 +#define IGD_MEMSIZE_128MB 0x04 + enum lpe_clk_src { LPE_CLK_SRC_XTAL, LPE_CLK_SRC_PLL,
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Felix Held (Code Review) -
Frans Hendriks (Code Review)
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Patrick Rudolph (Code Review)
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Paul Menzel (Code Review)