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Michał Żygowski has posted comments on this change by Michał Żygowski. ( https://review.coreboot.org/c/coreboot/+/83355?usp=email )
Change subject: superio/ite/common: Add common driver for GPIO and LED configuration ......................................................................
Patch Set 1:
(5 comments)
File src/mainboard/samsung/stumpy/smihandler.c:
https://review.coreboot.org/c/coreboot/+/83355/comment/746c6919_706f6218?usp... : PS1, Line 25: ite_reg_write(GPIO_DEV, IT8772F_GPIO_REG_SELECT(3), 0x20);
Now that these are seperate steps, the redundancy becomes obvious: We already […]
Yes, setup_sio_gpios already does it and further writes should not be necessary.
https://review.coreboot.org/c/coreboot/+/83355/comment/3d7d2f3b_843128ee?usp... : PS1, Line 49: ITE_LED_FREQ_1HZ);
This looks very odd now, configuring blink when it's not used? Traced […]
Right, enabling SIMPLE_IO_MODE in the ite_gpio_setup call should already disable the LED blinking function.
File src/superio/ite/common/gpio.c:
https://review.coreboot.org/c/coreboot/+/83355/comment/f8deb2d6_8f710df7?usp... : PS1, Line 130: */
It looks like IT8718F doesn't have pull-up set 2? […]
Right, I will revisit these datasheets and fix
File src/superio/ite/it8772f/it8772f.h:
https://review.coreboot.org/c/coreboot/+/83355/comment/abe24211_64d4e3d7?usp... : PS1, Line 16: : /* GPIO Polarity Select: 1: Inverting, 0: Non-inverting */ : #define IT8772F_GPIO_REG_POLARITY(x) (0xb0 + (x)) : : /* GPIO Internal Pull-up: 1: Enable, 0: Disable */ : #define IT8772F_GPIO_REG_PULLUP(x) (0xb8 + (x)) : : /* GPIO Function Select: 1: Simple I/O, 0: Alternate function */ : #define IT8772F_GPIO_REG_ENABLE(x) (0xc0 + (x)) : : /* GPIO Mode: 0: input mode, 1: output mode */ : #define IT8772F_GPIO_REG_OUTPUT(x) (0xc8 + (x)) :
Why keep them?
Forgot to leave IT8772F_GPIO_REG_SELECT only. But actually all ITE SIOs have these GPIO function selects starting at 0x25, so I will put it into superio/ite/common/ite_gpio.h
File src/superio/ite/it8786e/Kconfig:
https://review.coreboot.org/c/coreboot/+/83355/comment/ad4c4233_8f5ac068?usp... : PS1, Line 16: default 10
I only see 8?
In the "IT8786E-I Preliminary SPecification v0.4.1 for D version" section 8.10.10 there is a table of GPIO registers described for sets of up to 0xA (10).