HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46263 )
Change subject: nb/amd/pi/*/northbridge.c: Reduce difference ......................................................................
nb/amd/pi/*/northbridge.c: Reduce difference
Change-Id: I8d173916f38701d710a735cc12237bac6236ebab Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/amd/pi/00630F01/northbridge.c M src/northbridge/amd/pi/00660F01/northbridge.c M src/northbridge/amd/pi/00730F01/northbridge.c 3 files changed, 122 insertions(+), 103 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/46263/1
diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index 90d5603..ce0b23a 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -43,14 +43,14 @@ dev = __f1_dev[0]; u32 temp; temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16] - d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too - temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] - d.mask |= temp<<21; + d.mask = ((temp & 0xfff80000) >> (8 + 3)); // mask out DramMask [26:24] too + temp = pci_read_config32(dev, 0x144 + (nodeid << 3)) & 0xff; //[47:40] at [7:0] + d.mask |= temp << 21; temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16] d.mask |= (temp & 1); // enable bit - d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too - temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] - d.base |= temp<<21; + d.base = ((temp & 0xfff80000) >> (8 + 3)); // mask out DramBase [26:24) too + temp = pci_read_config32(dev, 0x140 + (nodeid << 3)) & 0xff; //[47:40] at [7:0] + d.base |= temp << 21; return d; }
@@ -60,10 +60,10 @@ u32 i; u32 tempreg; /* io range allocation */ - tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit + tempreg = (nodeid & 0xf) | ((nodeid & 0x30) << (8 - 4)) | (linkn << 4) | ((io_max & 0xf0)<<(12 - 4)); //limit for (i = 0; i < node_nums; i++) - pci_write_config32(__f1_dev[i], reg+4, tempreg); - tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? + pci_write_config32(__f1_dev[i], reg + 4, tempreg); + tempreg = 3 /*| (3<<4)*/ | ((io_min & 0xf0) << (12 - 4)); //base :ISA and VGA ? for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg, tempreg); } @@ -133,7 +133,7 @@ { u32 val;
- val = 1 | (nodeid<<4) | (linkn<<12); + val = 1 | (nodeid << 4) | (linkn<<12); /* it will routing * (1)mmio 0xa0000:0xbffff * (2)io 0x3b0:0x3bb, 0x3c0:0x3df @@ -148,8 +148,8 @@ * @retval 0 resource exists, but is not usable * @retval 1 resource exists, but has been allocated before */ -static int reg_useable(unsigned int reg, struct device *goal_dev, - unsigned int goal_nodeid, unsigned int goal_link) +static int reg_useable(unsigned int reg, struct device *goal_dev, unsigned int goal_nodeid, + unsigned int goal_link) { struct resource *res; unsigned int nodeid, link = 0; @@ -250,10 +250,12 @@ /* Initialize the prefetchable memory constraints on the current bus */ resource = amdfam15_find_mempair(dev, nodeid, link); if (resource) { + u32 align; + align = log2(HT_MEM_HOST_ALIGN); resource->base = 0; resource->size = 0; - resource->align = log2(HT_MEM_HOST_ALIGN); - resource->gran = log2(HT_MEM_HOST_ALIGN); + resource->align = align; + resource->gran = align; resource->limit = 0xffffffffffULL; resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; resource->flags |= IORESOURCE_BRIDGE; @@ -262,10 +264,12 @@ /* Initialize the memory constraints on the current bus */ resource = amdfam15_find_mempair(dev, nodeid, link); if (resource) { + u32 align; + align = log2(HT_MEM_HOST_ALIGN); resource->base = 0; resource->size = 0; - resource->align = log2(HT_MEM_HOST_ALIGN); - resource->gran = log2(HT_MEM_HOST_ALIGN); + resource->align = align; + resource->gran = align; resource->limit = 0xffffffffffULL; resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE; } @@ -299,23 +303,21 @@ char buf[50];
/* Make certain the resource has actually been set */ - if (!(resource->flags & IORESOURCE_ASSIGNED)) { + if (!(resource->flags & IORESOURCE_ASSIGNED)) return; - }
/* If I have already stored this resource don't worry about it */ - if (resource->flags & IORESOURCE_STORED) { + if (resource->flags & IORESOURCE_STORED) return; - }
/* Only handle PCI memory and IO resources */ if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO))) return;
/* Ensure I am actually looking at a resource of function 1 */ - if ((resource->index & 0xffff) < 0x1000) { + if ((resource->index & 0xffff) < 0x1000) return; - } + /* Get the base address */ rbase = resource->base;
@@ -382,7 +384,8 @@ /* Find the nodeid */ nodeid = amdfam15_nodeid(dev);
- create_vga_resource(dev, nodeid); //TODO: do we need this? + /* TODO: do we need this? */ + create_vga_resource(dev, nodeid);
/* Set each resource we have found */ for (res = dev->resource_list; res; res = res->next) { @@ -569,18 +572,18 @@
/* Find the already assigned resource pairs */ get_fx_devs(); - for (reg = 0x80; reg <= 0xd8; reg+= 0x08) { + for (reg = 0x80; reg <= 0xd8; reg += 0x08) { u32 base, limit; - base = f1_read_config32(reg); + base = f1_read_config32(reg); limit = f1_read_config32(reg + 0x04); /* Is this register allocated? */ if ((base & 3) != 0) { unsigned int nodeid, reg_link; struct device *reg_dev; if (reg < 0xc0) { // mmio - nodeid = (limit & 0xf) + (base&0x30); + nodeid = (limit & 0xf) + (base & 0x30); } else { // io - nodeid = (limit & 0xf) + ((base>>4)&0x30); + nodeid = (limit & 0xf) + ((base >> 4) & 0x30); } reg_link = (limit >> 4) & 7; reg_dev = __f0_dev[nodeid]; @@ -597,8 +600,7 @@ /* FIXME: do we need to check extend conf space? I don't believe that much preset value */
- pci_domain_read_resources(dev); - + pci_domain_read_resources(dev); }
static void domain_enable_resources(struct device *dev) @@ -622,7 +624,7 @@ d = get_dram_base_mask(i); if (!(d.mask & 1)) continue; // no memory on this node hole = pci_read_config32(__f1_dev[i], 0xf0); - if (hole & 1) { // we find the hole + if (hole & 1) { /* we find the hole */ mem_hole.hole_startk = (hole & (0xff<<24)) >> 10; mem_hole.node_id = i; // record the node No with hole break; // only one hole @@ -638,7 +640,8 @@ dram_base_mask_t d; resource_t base_k, limit_k; d = get_dram_base_mask(i); - if (!(d.base & 1)) continue; + if (!(d.base & 1)) + continue; base_k = ((resource_t)(d.base & 0x1fffff00)) <<9; if (base_k > 4 *1024 * 1024) break; // don't need to go to check if (limitk_pri != base_k) { // we find the hole @@ -675,8 +678,9 @@ /* Round mmio_basek to something the processor can support */ mmio_basek &= ~((1 << 6) -1);
- // FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M - // MMIO hole. If you fix this here, please fix amdk8, too. + /* FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M + * MMIO hole. If you fix this here, please fix amdk8, too. + */ /* Round the mmio hole to 64M */ mmio_basek &= ~((64*1024) - 1);
@@ -689,7 +693,7 @@
mem_hole = get_hw_mem_hole_info();
- // Use hole_basek as mmio_basek, and we don't need to reset hole anymore + /* Use hole_basek as mmio_basek, and we don't need to reset hole anymore */ if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) { mmio_basek = mem_hole.hole_startk; } @@ -702,7 +706,8 @@
d = get_dram_base_mask(i);
- if (!(d.mask & 1)) continue; + if (!(d.mask & 1)) + continue; basek = ((resource_t)(d.base & 0x1fffff00)) << 9; // could overflow, we may lost 6 bit here limitk = ((resource_t)(((d.mask & ~1) + 0x000FF) & 0x1fffff00)) << 9;
@@ -717,8 +722,6 @@
}
- //printk(BIOS_DEBUG, "node %d : mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); - /* split the region to accommodate pci memory space */ if ((basek < 4*1024*1024) && (limitk > mmio_basek)) { if (basek <= mmio_basek) { @@ -766,7 +769,7 @@ static void sysconf_init(struct device *dev) // first node { sblink = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1 - node_nums = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; //NodeCnt[2:0] + node_nums = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; // NodeCnt[2:0] }
static void cpu_bus_scan(struct device *dev) @@ -849,7 +852,8 @@ siblings &= 0xFF; } } else { - siblings = 0; //default one core + /* default one core */ + siblings = 0; } int enable_node = cdb_dev && cdb_dev->enabled; printk(BIOS_SPEW, "%s family%xh, core_max = 0x%x, core_nums = 0x%x, siblings = 0x%x\n", diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c index 09bdd82..594aebd 100644 --- a/src/northbridge/amd/pi/00660F01/northbridge.c +++ b/src/northbridge/amd/pi/00660F01/northbridge.c @@ -160,8 +160,9 @@ dev = __f0_dev[nodeid]; if (!dev) continue; - for (link = 0; !res && (link < 8); link++) + for (link = 0; !res && (link < 8); link++) { res = probe_resource(dev, IOINDEX(0x1000 + reg, link)); + } }
if (!res) @@ -226,10 +227,12 @@ /* Initialize the io space constraints on the current bus */ resource = amdfam15_find_iopair(dev, nodeid, link); if (resource) { + u32 align; + align = log2(HT_IO_HOST_ALIGN); resource->base = 0; resource->size = 0; - resource->align = log2(HT_IO_HOST_ALIGN); - resource->gran = log2(HT_IO_HOST_ALIGN); + resource->align = align; + resource->gran = align; resource->limit = 0xffffUL; resource->flags = IORESOURCE_IO | IORESOURCE_BRIDGE; } @@ -237,10 +240,12 @@ /* Initialize the prefetchable memory constraints on the current bus */ resource = amdfam15_find_mempair(dev, nodeid, link); if (resource) { + u32 align; + align = log2(HT_MEM_HOST_ALIGN); resource->base = 0; resource->size = 0; - resource->align = log2(HT_MEM_HOST_ALIGN); - resource->gran = log2(HT_MEM_HOST_ALIGN); + resource->align = align; + resource->gran = align; resource->limit = 0xffffffffffULL; resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; resource->flags |= IORESOURCE_BRIDGE; @@ -249,10 +254,12 @@ /* Initialize the memory constraints on the current bus */ resource = amdfam15_find_mempair(dev, nodeid, link); if (resource) { + u32 align; + align = log2(HT_MEM_HOST_ALIGN); resource->base = 0; resource->size = 0; - resource->align = log2(HT_MEM_HOST_ALIGN); - resource->gran = log2(HT_MEM_HOST_ALIGN); + resource->align = align; + resource->gran = align; resource->limit = 0xffffffffffULL; resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE; } @@ -336,14 +343,16 @@ * we only deal with the 'first' vga card */ for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { -#if CONFIG(MULTIPLE_VGA_ADAPTERS) - extern struct device *vga_pri; // the primary vga device, defined in device.c - printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, + if (CONFIG(MULTIPLE_VGA_ADAPTERS)) { + extern struct device *vga_pri; // the primary vga device, defined in device.c + printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); - /* We need to make sure the vga_pri is under the link */ - if ((vga_pri->bus->secondary >= link->secondary) && - (vga_pri->bus->secondary <= link->subordinate)) -#endif + /* We need to make sure the vga_pri is under the link */ + if ((vga_pri->bus->secondary >= link->secondary) && + (vga_pri->bus->secondary <= link->subordinate)) + break; + } + else break; } } @@ -365,7 +374,7 @@ /* Find the nodeid */ nodeid = amdfam15_nodeid(dev);
- /* do we need this? */ + /* TODO: do we need this? */ create_vga_resource(dev, nodeid);
/* Set each resource we have found */ @@ -624,8 +633,7 @@ d = get_dram_base_mask(i); if (!(d.mask & 1)) continue; // no memory on this node hole = pci_read_config32(__f1_dev[i], 0xf0); - if (hole & 2) { - /* we find the hole */ + if (hole & 2) { /* we find the hole */ mem_hole.hole_startk = (hole & (0xff<<24)) >> 10; mem_hole.node_id = i; // record the node No with hole break; // only one hole @@ -882,7 +890,7 @@ if ((node_nums * core_max) + ioapic_count >= 0x10) { lapicid_start = (ioapic_count - 1) / core_max; lapicid_start = (lapicid_start + 1) * core_max; - printk(BIOS_SPEW, "lpaicid_start = 0x%x ", lapicid_start); + printk(BIOS_SPEW, "lapicid_start = 0x%x ", lapicid_start); } u32 apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j); printk(BIOS_SPEW, "node 0x%x core 0x%x apicid = 0x%x\n", diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 75e1f02..16a98b7 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -50,14 +50,14 @@ dev = __f1_dev[0]; u32 temp; temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16] - d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too - temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] - d.mask |= temp<<21; + d.mask = ((temp & 0xfff80000) >> (8 + 3)); // mask out DramMask [26:24] too + temp = pci_read_config32(dev, 0x144 + (nodeid << 3)) & 0xff; //[47:40] at [7:0] + d.mask |= temp << 21; temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16] d.mask |= (temp & 1); // enable bit - d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too - temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] - d.base |= temp<<21; + d.base = ((temp & 0xfff80000) >> (8 + 3)); // mask out DramBase [26:24) too + temp = pci_read_config32(dev, 0x140 + (nodeid << 3)) & 0xff; //[47:40] at [7:0] + d.base |= temp << 21; return d; }
@@ -67,10 +67,10 @@ u32 i; u32 tempreg; /* io range allocation */ - tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit + tempreg = (nodeid & 0xf) | ((nodeid & 0x30) << (8 - 4)) | (linkn << 4) | ((io_max & 0xf0)<<(12 - 4)); //limit for (i = 0; i < node_nums; i++) - pci_write_config32(__f1_dev[i], reg+4, tempreg); - tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? + pci_write_config32(__f1_dev[i], reg + 4, tempreg); + tempreg = 3 /*| (3<<4)*/ | ((io_min & 0xf0) << (12 - 4)); //base :ISA and VGA ? for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg, tempreg); } @@ -140,7 +140,7 @@ { u32 val;
- val = 1 | (nodeid<<4) | (linkn<<12); + val = 1 | (nodeid << 4) | (linkn<<12); /* it will routing * (1)mmio 0xa0000:0xbffff * (2)io 0x3b0:0x3bb, 0x3c0:0x3df @@ -155,8 +155,8 @@ * @retval 0 resource exists, not usable * @retval 1 resource exist, resource has been allocated before */ -static int reg_useable(unsigned int reg, struct device *goal_dev, - unsigned int goal_nodeid, unsigned int goal_link) +static int reg_useable(unsigned int reg, struct device *goal_dev, unsigned int goal_nodeid, + unsigned int goal_link) { struct resource *res; unsigned int nodeid, link = 0; @@ -257,10 +257,12 @@ /* Initialize the prefetchable memory constraints on the current bus */ resource = amdfam16_find_mempair(dev, nodeid, link); if (resource) { + u32 align; + align = log2(HT_MEM_HOST_ALIGN); resource->base = 0; resource->size = 0; - resource->align = log2(HT_MEM_HOST_ALIGN); - resource->gran = log2(HT_MEM_HOST_ALIGN); + resource->align = align; + resource->gran = align; resource->limit = 0xffffffffffULL; resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; resource->flags |= IORESOURCE_BRIDGE; @@ -269,10 +271,12 @@ /* Initialize the memory constraints on the current bus */ resource = amdfam16_find_mempair(dev, nodeid, link); if (resource) { + u32 align; + align = log2(HT_MEM_HOST_ALIGN); resource->base = 0; resource->size = 0; - resource->align = log2(HT_MEM_HOST_ALIGN); - resource->gran = log2(HT_MEM_HOST_ALIGN); + resource->align = align; + resource->gran = align; resource->limit = 0xffffffffffULL; resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE; } @@ -313,23 +317,21 @@ char buf[50];
/* Make certain the resource has actually been set */ - if (!(resource->flags & IORESOURCE_ASSIGNED)) { + if (!(resource->flags & IORESOURCE_ASSIGNED)) return; - }
/* If I have already stored this resource don't worry about it */ - if (resource->flags & IORESOURCE_STORED) { + if (resource->flags & IORESOURCE_STORED) return; - }
/* Only handle PCI memory and IO resources */ if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO))) return;
/* Ensure I am actually looking at a resource of function 1 */ - if ((resource->index & 0xffff) < 0x1000) { + if ((resource->index & 0xffff) < 0x1000) return; - } + /* Get the base address */ rbase = resource->base;
@@ -365,14 +367,16 @@ * we only deal with the 'first' vga card */ for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { -#if CONFIG(MULTIPLE_VGA_ADAPTERS) - extern struct device *vga_pri; // the primary vga device, defined in device.c - printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, + if (CONFIG(MULTIPLE_VGA_ADAPTERS)) { + extern struct device *vga_pri; // the primary vga device, defined in device.c + printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); - /* We need to make sure the vga_pri is under the link */ - if ((vga_pri->bus->secondary >= link->secondary) && - (vga_pri->bus->secondary <= link->subordinate)) -#endif + /* We need to make sure the vga_pri is under the link */ + if ((vga_pri->bus->secondary >= link->secondary) && + (vga_pri->bus->secondary <= link->subordinate)) + break; + } + else break; } } @@ -394,7 +398,8 @@ /* Find the nodeid */ nodeid = amdfam16_nodeid(dev);
- create_vga_resource(dev, nodeid); //TODO: do we need this? + /* TODO: do we need this? */ + create_vga_resource(dev, nodeid);
/* Set each resource we have found */ for (res = dev->resource_list; res; res = res->next) { @@ -925,18 +930,18 @@
/* Find the already assigned resource pairs */ get_fx_devs(); - for (reg = 0x80; reg <= 0xd8; reg+= 0x08) { + for (reg = 0x80; reg <= 0xd8; reg += 0x08) { u32 base, limit; - base = f1_read_config32(reg); + base = f1_read_config32(reg); limit = f1_read_config32(reg + 0x04); /* Is this register allocated? */ if ((base & 3) != 0) { unsigned int nodeid, reg_link; struct device *reg_dev; if (reg < 0xc0) { // mmio - nodeid = (limit & 0xf) + (base&0x30); + nodeid = (limit & 0xf) + (base & 0x30); } else { // io - nodeid = (limit & 0xf) + ((base>>4)&0x30); + nodeid = (limit & 0xf) + ((base >> 4) & 0x30); } reg_link = (limit >> 4) & 7; reg_dev = __f0_dev[nodeid]; @@ -952,6 +957,7 @@ } /* FIXME: do we need to check extend conf space? I don't believe that much preset value */ + pci_domain_read_resources(dev); }
@@ -976,7 +982,7 @@ d = get_dram_base_mask(i); if (!(d.mask & 1)) continue; // no memory on this node hole = pci_read_config32(__f1_dev[i], 0xf0); - if (hole & 2) { // we find the hole + if (hole & 2) { /* we find the hole */ mem_hole.hole_startk = (hole & (0xff<<24)) >> 10; mem_hole.node_id = i; // record the node No with hole break; // only one hole @@ -992,7 +998,8 @@ dram_base_mask_t d; resource_t base_k, limit_k; d = get_dram_base_mask(i); - if (!(d.base & 1)) continue; + if (!(d.base & 1)) + continue; base_k = ((resource_t)(d.base & 0x1fffff00)) <<9; if (base_k > 4 *1024 * 1024) break; // don't need to go to check if (limitk_pri != base_k) { // we find the hole @@ -1029,8 +1036,9 @@ /* Round mmio_basek to something the processor can support */ mmio_basek &= ~((1 << 6) -1);
- // FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M - // MMIO hole. If you fix this here, please fix amdk8, too. + /* FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M + * MMIO hole. If you fix this here, please fix amdk8, too. + */ /* Round the mmio hole to 64M */ mmio_basek &= ~((64*1024) - 1);
@@ -1043,7 +1051,7 @@
mem_hole = get_hw_mem_hole_info();
- // Use hole_basek as mmio_basek, and we don't need to reset hole anymore + /* Use hole_basek as mmio_basek, and we don't need to reset hole anymore */ if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) { mmio_basek = mem_hole.hole_startk; } @@ -1056,7 +1064,8 @@
d = get_dram_base_mask(i);
- if (!(d.mask & 1)) continue; + if (!(d.mask & 1)) + continue; basek = ((resource_t)(d.base & 0x1fffff00)) << 9; // could overflow, we may lost 6 bit here limitk = ((resource_t)(((d.mask & ~1) + 0x000FF) & 0x1fffff00)) << 9;
@@ -1071,8 +1080,6 @@
}
- //printk(BIOS_DEBUG, "node %d : mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); - /* split the region to accommodate pci memory space */ if ((basek < 4*1024*1024) && (limitk > mmio_basek)) { if (basek <= mmio_basek) { @@ -1129,7 +1136,7 @@ static void sysconf_init(struct device *dev) // first node { sblink = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1 - node_nums = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; //NodeCnt[2:0] + node_nums = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; // NodeCnt[2:0] }
static void cpu_bus_scan(struct device *dev) @@ -1195,7 +1202,6 @@ /* Ok, We need to set the links for that device. * otherwise the device under it will not be scanned */ - add_more_links(cdb_dev, 4); }
@@ -1213,7 +1219,8 @@ siblings &= 0xFF; } } else { - siblings = 0; //default one core + /* default one core */ + siblings = 0; } int enable_node = cdb_dev && cdb_dev->enabled; printk(BIOS_SPEW, "%s family%xh, core_max = 0x%x, core_nums = 0x%x, siblings = 0x%x\n", @@ -1238,7 +1245,7 @@ if ((node_nums * core_max) + ioapic_count >= 0x10) { lapicid_start = (ioapic_count - 1) / core_max; lapicid_start = (lapicid_start + 1) * core_max; - printk(BIOS_SPEW, "lpaicid_start = 0x%x ", lapicid_start); + printk(BIOS_SPEW, "lapicid_start = 0x%x ", lapicid_start); } u32 apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j); printk(BIOS_SPEW, "node 0x%x core 0x%x apicid = 0x%x\n",
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46263 )
Change subject: nb/amd/pi/*/northbridge.c: Reduce difference ......................................................................
Patch Set 1:
(9 comments)
https://review.coreboot.org/c/coreboot/+/46263/1/src/northbridge/amd/pi/0063... File src/northbridge/amd/pi/00630F01/northbridge.c:
https://review.coreboot.org/c/coreboot/+/46263/1/src/northbridge/amd/pi/0063... PS1, Line 63: tempreg = (nodeid & 0xf) | ((nodeid & 0x30) << (8 - 4)) | (linkn << 4) | ((io_max & 0xf0)<<(12 - 4)); //limit line over 96 characters
https://review.coreboot.org/c/coreboot/+/46263/1/src/northbridge/amd/pi/0066... File src/northbridge/amd/pi/00660F01/northbridge.c:
https://review.coreboot.org/c/coreboot/+/46263/1/src/northbridge/amd/pi/0066... PS1, Line 163: for (link = 0; !res && (link < 8); link++) { braces {} are not necessary for single statement blocks
https://review.coreboot.org/c/coreboot/+/46263/1/src/northbridge/amd/pi/0066... PS1, Line 347: extern struct device *vga_pri; // the primary vga device, defined in device.c line over 96 characters
https://review.coreboot.org/c/coreboot/+/46263/1/src/northbridge/amd/pi/0066... PS1, Line 348: printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, line over 96 characters
https://review.coreboot.org/c/coreboot/+/46263/1/src/northbridge/amd/pi/0066... PS1, Line 355: else else should follow close brace '}'
https://review.coreboot.org/c/coreboot/+/46263/1/src/northbridge/amd/pi/0073... File src/northbridge/amd/pi/00730F01/northbridge.c:
https://review.coreboot.org/c/coreboot/+/46263/1/src/northbridge/amd/pi/0073... PS1, Line 70: tempreg = (nodeid & 0xf) | ((nodeid & 0x30) << (8 - 4)) | (linkn << 4) | ((io_max & 0xf0)<<(12 - 4)); //limit line over 96 characters
https://review.coreboot.org/c/coreboot/+/46263/1/src/northbridge/amd/pi/0073... PS1, Line 371: extern struct device *vga_pri; // the primary vga device, defined in device.c line over 96 characters
https://review.coreboot.org/c/coreboot/+/46263/1/src/northbridge/amd/pi/0073... PS1, Line 372: printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, line over 96 characters
https://review.coreboot.org/c/coreboot/+/46263/1/src/northbridge/amd/pi/0073... PS1, Line 379: else else should follow close brace '}'
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46263 )
Change subject: nb/amd/pi/*/northbridge.c: Reduce difference ......................................................................
Patch Set 1:
This change is ready for review.
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46263 )
Change subject: nb/amd/pi/*/northbridge.c: Reduce difference ......................................................................
Patch Set 2:
(5 comments)
https://review.coreboot.org/c/coreboot/+/46263/2/src/northbridge/amd/pi/0066... File src/northbridge/amd/pi/00660F01/northbridge.c:
https://review.coreboot.org/c/coreboot/+/46263/2/src/northbridge/amd/pi/0066... PS2, Line 165: for (link = 0; !res && (link < 8); link++) { braces {} are not necessary for single statement blocks
https://review.coreboot.org/c/coreboot/+/46263/2/src/northbridge/amd/pi/0066... PS2, Line 360: else else should follow close brace '}'
https://review.coreboot.org/c/coreboot/+/46263/2/src/northbridge/amd/pi/0073... File src/northbridge/amd/pi/00730F01/northbridge.c:
https://review.coreboot.org/c/coreboot/+/46263/2/src/northbridge/amd/pi/0073... PS2, Line 179: if ((goal_link == (link - 1)) && trailing whitespace
https://review.coreboot.org/c/coreboot/+/46263/2/src/northbridge/amd/pi/0073... PS2, Line 384: else else should follow close brace '}'
https://review.coreboot.org/c/coreboot/+/46263/2/src/northbridge/amd/pi/0073... PS2, Line 1308: new_vendev = ((0x10029850 <= vendev) && (vendev <= 0x1002986F)) ? 0x10029850 : vendev; Comparisons should place the constant on the right side of the test
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46263
to look at the new patch set (#3).
Change subject: nb/amd/pi/*/northbridge.c: Reduce difference ......................................................................
nb/amd/pi/*/northbridge.c: Reduce difference
Change-Id: I8d173916f38701d710a735cc12237bac6236ebab Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/amd/pi/00630F01/northbridge.c M src/northbridge/amd/pi/00660F01/northbridge.c M src/northbridge/amd/pi/00730F01/northbridge.c 3 files changed, 253 insertions(+), 214 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/46263/3
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46263 )
Change subject: nb/amd/pi/*/northbridge.c: Reduce difference ......................................................................
Patch Set 3:
(4 comments)
https://review.coreboot.org/c/coreboot/+/46263/3/src/northbridge/amd/pi/0066... File src/northbridge/amd/pi/00660F01/northbridge.c:
https://review.coreboot.org/c/coreboot/+/46263/3/src/northbridge/amd/pi/0066... PS3, Line 165: for (link = 0; !res && (link < 8); link++) { braces {} are not necessary for single statement blocks
https://review.coreboot.org/c/coreboot/+/46263/3/src/northbridge/amd/pi/0066... PS3, Line 360: else else should follow close brace '}'
https://review.coreboot.org/c/coreboot/+/46263/3/src/northbridge/amd/pi/0073... File src/northbridge/amd/pi/00730F01/northbridge.c:
https://review.coreboot.org/c/coreboot/+/46263/3/src/northbridge/amd/pi/0073... PS3, Line 384: else else should follow close brace '}'
https://review.coreboot.org/c/coreboot/+/46263/3/src/northbridge/amd/pi/0073... PS3, Line 1308: new_vendev = ((0x10029850 <= vendev) && (vendev <= 0x1002986F)) ? 0x10029850 : vendev; Comparisons should place the constant on the right side of the test
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46263
to look at the new patch set (#4).
Change subject: nb/amd/pi/*/northbridge.c: Reduce difference ......................................................................
nb/amd/pi/*/northbridge.c: Reduce difference
Change-Id: I8d173916f38701d710a735cc12237bac6236ebab Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/amd/pi/00630F01/northbridge.c M src/northbridge/amd/pi/00730F01/northbridge.c 2 files changed, 183 insertions(+), 159 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/46263/4
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46263 )
Change subject: nb/amd/pi/*/northbridge.c: Reduce difference ......................................................................
Patch Set 4:
(2 comments)
File src/northbridge/amd/pi/00730F01/northbridge.c:
https://review.coreboot.org/c/coreboot/+/46263/comment/acfb2b9a_4e4942ce PS4, Line 383: else else should follow close brace '}'
https://review.coreboot.org/c/coreboot/+/46263/comment/cfa68aa9_92407b95 PS4, Line 1307: new_vendev = ((0x10029850 <= vendev) && (vendev <= 0x1002986F)) ? 0x10029850 : vendev; Comparisons should place the constant on the right side of the test
-
build bot (Jenkins) (Code Review) -
HAOUAS Elyes (Code Review)