Change in ...coreboot[master]: nb/intel/gm45: Correctly cache TSEG - coreboot-gerrit

27 Nov 2018


      Hello Patrick Rudolph, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/29866
to look at the new patch set (#4).
Change subject: nb/intel/gm45: Correctly cache TSEG
......................................................................
nb/intel/gm45: Correctly cache TSEG
Change-Id: I6a8752da9f92b90a2cb2cca5ebf28e2bc5a9c9a8
Signed-off-by: Arthur Heymans arthur@aheymans.xyz
---
M src/northbridge/intel/gm45/gm45.h
M src/northbridge/intel/gm45/northbridge.c
M src/northbridge/intel/gm45/ram_calc.c
3 files changed, 14 insertions(+), 22 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/29866/4
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I6a8752da9f92b90a2cb2cca5ebf28e2bc5a9c9a8
Gerrit-Change-Number: 29866
Gerrit-PatchSet: 4
Gerrit-Owner: Arthur Heymans arthur@aheymans.xyz
Gerrit-Reviewer: Arthur Heymans arthur@aheymans.xyz
Gerrit-Reviewer: Nico Huber nico.h@gmx.de
Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org
Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org
Gerrit-MessageType: newpatchset