[XS] Change in coreboot[master]: soc/amd/common/psp_verstage: Perform Legacy IO enable on older SoCs

[Karthik Ramasubramanian (Code Review)]

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Karthik Ramasubramanian, Martin Roth, Matt DeVillier, Raul Rangel.

Hello Felix Held, Fred Reitberger, Jason Glenesk, Martin Roth, Matt DeVillier, Raul Rangel, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/76692?usp=email

to look at the new patch set (#4).

The following approvals got outdated and were removed:
Code-Review+1 by Felix Held, Code-Review+2 by Martin Roth, Verified+1 by build bot (Jenkins)

Change subject: soc/amd/common/psp_verstage: Perform Legacy IO enable on older SoCs
......................................................................

soc/amd/common/psp_verstage: Perform Legacy IO enable on older SoCs

With reference to the Picasso PPR 55570 Rev 3.18, LegacyIoEn bit is 0 on
reset and setting it will enable the decoding of the following legacy IO
ports:
0x20, 0x21, 0xA0, 0xA1 (PIC);
0x40, 0x41, 0x42, 0x43, 0x61 (8254 timer);
0x70, 0x71, 0x72, 0x73 (RTC);
0x92.

Verstage does not use those legacy IO ports. Also newer SoCs like
Phoenix do not support Legacy I/O registers to access Power Management
registers. Hence enable legacy IO only on platforms that support it.

BUG=b::284984667
TEST=Build Myst BIOS image with PSP Verstage. Boot to OS successfully
with PSP verstage.

Change-Id: I5e74b4cd1fa7e942770976e5e2197ded47503660
Signed-off-by: Karthikeyan Ramasubramanian 
---
M src/soc/amd/common/psp_verstage/psp_verstage.c
1 file changed, 2 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/76692/4