Change in coreboot[master]: cpu/amd/agesa/family15tn/model_15_init.c: create correct MTRR solution

[Arthur Heymans (Code Review)]

Attention is currently required from: Michał Żygowski, Angel Pons, Arthur Heymans, Felix Held.
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/53991 )

Change subject: cpu/amd/agesa/family15tn/model_15_init.c: create correct MTRR solution
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Patch Set 3:

(1 comment)

File src/cpu/amd/agesa/family15tn/model_15_init.c:

https://review.coreboot.org/c/coreboot/+/53991/comment/e1b45821_61d1544a 
PS3, Line 39: execution
> Yes, I probably meant AGESA, because I recall having a longer execution time of AmdInitLate. But shouldn't ROM MTRR rather be included in postcar frame instead?

Postcar frame MTRR are not the same one as the final ones. They are just a solution to speed up early ramstage.

Whether a RO MTRR for ROM is a good idea depends a bit on the hardware. After romstage everything gets copied to dram/cbmem and executed there. In the postcar frame you set up MTRR for dram to WB and sometimes also a RO MTRR to speed up flash access. This is not universally a speed-up and on some platforms it actually slows things down. I guess the only thing still read from flash after CPU init is the payload. Do you see a speedup at loading the payload using a RO MTRR to cover the flash?