Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46788 )
Change subject: nb/intel/haswell/acpi/hostbridge.asl: Drop unused registers ......................................................................
nb/intel/haswell/acpi/hostbridge.asl: Drop unused registers
These are not used anywhere and are not present on Broadwell.
Change-Id: I2d1359286ac719cb5daefc955d5c6085e2949c1f Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/haswell/acpi/hostbridge.asl 1 file changed, 0 insertions(+), 61 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/46788/1
diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl index 08f4471..534ff7f 100644 --- a/src/northbridge/intel/haswell/acpi/hostbridge.asl +++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl @@ -12,71 +12,10 @@ OperationRegion (MCHP, PCI_Config, 0x00, 0x100) Field (MCHP, DWordAcc, NoLock, Preserve) { - Offset (0x40), // EPBAR - EPEN, 1, // Enable - , 11, // - EPBR, 27, // EPBAR - - Offset (0x48), // MCHBAR - MHEN, 1, // Enable - , 14, // - MHBR, 24, // MCHBAR - Offset (0x54), - DVEN, 32, - Offset (0x60), // PCIe BAR - PXEN, 1, // Enable - PXSZ, 2, // BAR size - , 23, // - PXBR, 13, // PCIe BAR - - Offset (0x68), // DMIBAR - DMEN, 1, // Enable - , 11, // - DMBR, 27, // DMIBAR - Offset (0x70), // ME Base Address MEBA, 64, - - // ... - - Offset (0x80), // PAM0 - , 4, - PM0H, 2, - , 2, - Offset (0x81), // PAM1 - PM1L, 2, - , 2, - PM1H, 2, - , 2, - Offset (0x82), // PAM2 - PM2L, 2, - , 2, - PM2H, 2, - , 2, - Offset (0x83), // PAM3 - PM3L, 2, - , 2, - PM3H, 2, - , 2, - Offset (0x84), // PAM4 - PM4L, 2, - , 2, - PM4H, 2, - , 2, - Offset (0x85), // PAM5 - PM5L, 2, - , 2, - PM5H, 2, - , 2, - Offset (0x86), // PAM6 - PM6L, 2, - , 2, - PM6H, 2, - , 2, - Offset (0xa0), // Top of Used Memory TOM, 64, - Offset (0xbc), // Top of Low Used Memory TLUD, 32, }
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46788 )
Change subject: nb/intel/haswell/acpi/hostbridge.asl: Drop unused registers ......................................................................
Patch Set 8: Code-Review+2
Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46788 )
Change subject: nb/intel/haswell/acpi/hostbridge.asl: Drop unused registers ......................................................................
nb/intel/haswell/acpi/hostbridge.asl: Drop unused registers
These are not used anywhere and are not present on Broadwell.
Change-Id: I2d1359286ac719cb5daefc955d5c6085e2949c1f Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/46788 Reviewed-by: Michael Niewöhner foss@mniewoehner.de Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/northbridge/intel/haswell/acpi/hostbridge.asl 1 file changed, 0 insertions(+), 61 deletions(-)
Approvals: build bot (Jenkins): Verified Michael Niewöhner: Looks good to me, approved
diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl index dc3a36f..f0cb86b 100644 --- a/src/northbridge/intel/haswell/acpi/hostbridge.asl +++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl @@ -12,71 +12,10 @@ OperationRegion (MCHP, PCI_Config, 0x00, 0x100) Field (MCHP, DWordAcc, NoLock, Preserve) { - Offset (0x40), // EPBAR - EPEN, 1, // Enable - , 11, // - EPBR, 27, // EPBAR - - Offset (0x48), // MCHBAR - MHEN, 1, // Enable - , 14, // - MHBR, 24, // MCHBAR - Offset (0x54), - DVEN, 32, - Offset (0x60), // PCIe BAR - PXEN, 1, // Enable - PXSZ, 2, // BAR size - , 23, // - PXBR, 13, // PCIe BAR - - Offset (0x68), // DMIBAR - DMEN, 1, // Enable - , 11, // - DMBR, 27, // DMIBAR - Offset (0x70), // ME Base Address MEBA, 64, - - // ... - - Offset (0x80), // PAM0 - , 4, - PM0H, 2, - , 2, - Offset (0x81), // PAM1 - PM1L, 2, - , 2, - PM1H, 2, - , 2, - Offset (0x82), // PAM2 - PM2L, 2, - , 2, - PM2H, 2, - , 2, - Offset (0x83), // PAM3 - PM3L, 2, - , 2, - PM3H, 2, - , 2, - Offset (0x84), // PAM4 - PM4L, 2, - , 2, - PM4H, 2, - , 2, - Offset (0x85), // PAM5 - PM5L, 2, - , 2, - PM5H, 2, - , 2, - Offset (0x86), // PAM6 - PM6L, 2, - , 2, - PM6H, 2, - , 2, - Offset (0xa0), // Top of Used Memory TOM, 64, - Offset (0xbc), // Top of Low Used Memory TLUD, 32, }
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Angel Pons (Code Review) -
Michael Niewöhner (Code Review)