Yuchen He has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/76045?usp=email )
Change subject: include/intelblocks/post_code.h: Change post code prefix to POSTCODE ......................................................................
include/intelblocks/post_code.h: Change post code prefix to POSTCODE
The prefix POSTCODE makes it clear that the macro is a post code. Hence, replace related macros starting with POST to POSTCODE and also replace every instance the macros are invoked with the new name.
The files was changed by running the following bash script from the top level directory.
filedir=src/soc/intel/common/block/include/intelblocks/post_codes.h sed -i'' '1,${s/#define POST_/#define POSTCODE_/g;}' $filedir myArray=`grep -e "^#define POSTCODE_" $filedir | grep -v "POST_CODES_H" | tr '\t' ' ' | cut -d ' ' -f 2` for str in ${myArray[@]}; do splitstr=`echo $str | cut -d '_' -f2-` grep -r POST_$splitstr src | cut -d ':' -f 1 | xargs sed -i'' -e "s/POST_$splitstr/$str/g" done
Change-Id: Ie84abb6cfd467dd51c0d62111306969ecab5313b Signed-off-by: lilacious yuchenhe126@gmail.com --- M src/drivers/amd/agesa/cache_as_ram.S M src/soc/amd/common/block/cpu/car/cache_as_ram.S M src/soc/amd/common/block/cpu/noncar/pre_c.S M src/soc/amd/common/block/include/amdblocks/post_codes.h M src/soc/intel/common/block/cpu/car/cache_as_ram.S M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/include/intelblocks/post_codes.h 7 files changed, 25 insertions(+), 25 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/76045/1
diff --git a/src/drivers/amd/agesa/cache_as_ram.S b/src/drivers/amd/agesa/cache_as_ram.S index 9fd1a0a..b287eca 100644 --- a/src/drivers/amd/agesa/cache_as_ram.S +++ b/src/drivers/amd/agesa/cache_as_ram.S @@ -31,7 +31,7 @@ */ bootblock_pre_c_entry:
- post_code(POST_BOOTBLOCK_PRE_C_ENTRY) + post_code(POSTCODE_BOOTBLOCK_PRE_C_ENTRY)
AMD_ENABLE_STACK
diff --git a/src/soc/amd/common/block/cpu/car/cache_as_ram.S b/src/soc/amd/common/block/cpu/car/cache_as_ram.S index 372f515..63342a7 100644 --- a/src/soc/amd/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/amd/common/block/cpu/car/cache_as_ram.S @@ -28,7 +28,7 @@ .global bootblock_pre_c_entry bootblock_pre_c_entry:
- post_code(POST_BOOTBLOCK_PRE_C_ENTRY) + post_code(POSTCODE_BOOTBLOCK_PRE_C_ENTRY)
AMD_ENABLE_STACK
diff --git a/src/soc/amd/common/block/cpu/noncar/pre_c.S b/src/soc/amd/common/block/cpu/noncar/pre_c.S index 72d7788..bc5f8d9 100644 --- a/src/soc/amd/common/block/cpu/noncar/pre_c.S +++ b/src/soc/amd/common/block/cpu/noncar/pre_c.S @@ -24,7 +24,7 @@
.global bootblock_pre_c_entry bootblock_pre_c_entry: - post_code(POST_BOOTBLOCK_PRE_C_ENTRY) + post_code(POSTCODE_BOOTBLOCK_PRE_C_ENTRY)
#if ENV_X86_64 #include <cpu/x86/64bit/entry64.inc> diff --git a/src/soc/amd/common/block/include/amdblocks/post_codes.h b/src/soc/amd/common/block/include/amdblocks/post_codes.h index 5251769..dbd546f 100644 --- a/src/soc/amd/common/block/include/amdblocks/post_codes.h +++ b/src/soc/amd/common/block/include/amdblocks/post_codes.h @@ -27,7 +27,7 @@
#define POST_BOOTBLOCK_RESUME_ENTRY 0xb0 -#define POST_BOOTBLOCK_PRE_C_ENTRY 0xa0 +#define POSTCODE_BOOTBLOCK_PRE_C_ENTRY 0xa0 #define POST_BOOTBLOCK_PRE_C_DONE 0xa2
#endif diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index 1b393d41..3c8dc2e 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -78,7 +78,7 @@ .global bootblock_pre_c_entry bootblock_pre_c_entry:
- post_code(POST_BOOTBLOCK_PRE_C_ENTRY) + post_code(POSTCODE_BOOTBLOCK_PRE_C_ENTRY)
/* Bootguard sets up its own CAR and needs separate handling */ check_boot_guard: @@ -98,7 +98,7 @@ jmp check_mtrr /* Check if CPU properly reset */
no_reset: - post_code(POST_SOC_NO_RESET) + post_code(POSTCODE_SOC_NO_RESET)
/* Clear/disable fixed MTRRs */ mov $fixed_mtrr_list, %ebx @@ -130,7 +130,7 @@ dec %ebx jnz clear_var_mtrr
- post_code(POST_SOC_CLEAR_VAR_MTRRS) + post_code(POSTCODE_SOC_CLEAR_VAR_MTRRS)
/* Configure default memory type to uncacheable (UC) */ mov $MTRR_DEF_TYPE_MSR, %ecx @@ -158,7 +158,7 @@ bts %eax, %esi dec %esi /* esi <- MTRR_PHYS_MASK_HIGH */
- post_code(POST_SOC_SET_UP_CAR_MTRRS) + post_code(POSTCODE_SOC_SET_UP_CAR_MTRRS)
#if ((CONFIG_DCACHE_RAM_SIZE & (CONFIG_DCACHE_RAM_SIZE - 1)) == 0) find_free_mtrr @@ -217,7 +217,7 @@ #else #error "DCACHE_RAM_SIZE is not a power of 2 and setup code is missing" #endif - post_code(POST_SOC_BOOTGUARD_SETUP) + post_code(POSTCODE_SOC_BOOTGUARD_SETUP)
is_bootguard_nem jz no_bootguard_car_continue @@ -269,7 +269,7 @@ .global car_init_done car_init_done:
- post_code(POST_SOC_CAR_INIT_DONE) + post_code(POSTCODE_SOC_CAR_INIT_DONE)
/* Setup bootblock stack */ mov $_ecar_stack, %esp @@ -296,7 +296,7 @@ #endif
before_carstage: - post_code(POST_SOC_BEFORE_CARSTAGE) + post_code(POSTCODE_SOC_BEFORE_CARSTAGE)
call bootblock_c_entry /* Never reached */ @@ -329,7 +329,7 @@ or $0x1, %eax wrmsr
- post_code(POST_SOC_CLEARING_CAR) + post_code(POSTCODE_SOC_CLEARING_CAR)
clear_car
@@ -418,7 +418,7 @@ and %ebx, %eax wrmsr
- post_code(POST_SOC_CLEARING_CAR) + post_code(POSTCODE_SOC_CLEARING_CAR)
clear_car
@@ -447,7 +447,7 @@ rdmsr or $0x1, %eax wrmsr - post_code(POST_SOC_CAR_NEM_ENHANCED) + post_code(POSTCODE_SOC_CAR_NEM_ENHANCED)
/* Create n-way set associativity of cache */ xorl %edi, %edi diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index ea956a7..7f53007 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -610,7 +610,7 @@ uint32_t csr;
/* Clear post code to prevent eventlog entry from unknown code. */ - post_code(POST_CODE_ZERO); + post_code(POSTCODE_ZERO);
/* Send reset request */ csr = read_host_csr(); diff --git a/src/soc/intel/common/block/include/intelblocks/post_codes.h b/src/soc/intel/common/block/include/intelblocks/post_codes.h index b04b1ac..c4cd2ab 100644 --- a/src/soc/intel/common/block/include/intelblocks/post_codes.h +++ b/src/soc/intel/common/block/include/intelblocks/post_codes.h @@ -4,18 +4,18 @@ #define SOC_INTEL_COMMON_BLOCK_POST_CODES_H
/* common/block/cpu/car/cache_as_ram.s */ -#define POST_BOOTBLOCK_PRE_C_ENTRY 0x20 -#define POST_SOC_NO_RESET 0x21 +#define POSTCODE_BOOTBLOCK_PRE_C_ENTRY 0x20 +#define POSTCODE_SOC_NO_RESET 0x21 #define POSTCODE_SOC_CLEAR_FIXED_MTRRS 0x22 -#define POST_SOC_CLEAR_VAR_MTRRS 0x23 -#define POST_SOC_SET_UP_CAR_MTRRS 0x24 -#define POST_SOC_BOOTGUARD_SETUP 0x25 -#define POST_SOC_CLEARING_CAR 0x26 +#define POSTCODE_SOC_CLEAR_VAR_MTRRS 0x23 +#define POSTCODE_SOC_SET_UP_CAR_MTRRS 0x24 +#define POSTCODE_SOC_BOOTGUARD_SETUP 0x25 +#define POSTCODE_SOC_CLEARING_CAR 0x26 #define POSTCODE_SOC_DISABLE_CACHE_EVICT 0x27 -#define POST_SOC_CAR_NEM_ENHANCED 0x28 -#define POST_SOC_CAR_INIT_DONE 0x29 -#define POST_SOC_BEFORE_CARSTAGE 0x2a +#define POSTCODE_SOC_CAR_NEM_ENHANCED 0x28 +#define POSTCODE_SOC_CAR_INIT_DONE 0x29 +#define POSTCODE_SOC_BEFORE_CARSTAGE 0x2a
/* common/block/cse/cse.c */ -#define POST_CODE_ZERO 0x00 +#define POSTCODE_CODE_ZERO 0x00 #endif