Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44275 )
Change subject: soc/intel/common/block/gspi: Clear the GSPI controller data ......................................................................
soc/intel/common/block/gspi: Clear the GSPI controller data
Clear the GSPI controller data after resource allocation. This will ensure that any early BAR cached by the GSPI controller driver is cleared. This will allow using GSPI before and after resource allocation in ramstage.
BUG=b:154333137 TEST=Ensure that the device boots to OS. Ensure that the TPM initialization is successful before and after resource allocation stage in ramstage.
Change-Id: I4444266e35cca54e2c9bd9221733e59737ad8ebd Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com --- M src/soc/intel/common/block/gspi/gspi.c 1 file changed, 7 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/44275/1
diff --git a/src/soc/intel/common/block/gspi/gspi.c b/src/soc/intel/common/block/gspi/gspi.c index 599ab7e..10dd504 100644 --- a/src/soc/intel/common/block/gspi/gspi.c +++ b/src/soc/intel/common/block/gspi/gspi.c @@ -2,6 +2,7 @@
#include <device/mmio.h> #include <assert.h> +#include <bootstate.h> #include <console/console.h> #include <delay.h> #include <device/device.h> @@ -725,3 +726,9 @@ .xfer = gspi_ctrlr_xfer, .max_xfer_size = SPI_CTRLR_DEFAULT_MAX_XFER_SIZE, }; + +static void gspi_clear_base_stash(void *unused) +{ + memset(gspi_base, 0, sizeof(gspi_base)); +} +BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT, gspi_clear_base_stash, NULL);
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44275 )
Change subject: soc/intel/common/block/gspi: Clear the GSPI controller data ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44275/1/src/soc/intel/common/block/... File src/soc/intel/common/block/gspi/gspi.c:
https://review.coreboot.org/c/coreboot/+/44275/1/src/soc/intel/common/block/... PS1, Line 732: memset(gspi_base, 0, sizeof(gspi_base)); please, no spaces at the start of a line
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44275
to look at the new patch set (#2).
Change subject: soc/intel/common/block/gspi: Clear the GSPI controller data ......................................................................
soc/intel/common/block/gspi: Clear the GSPI controller data
Clear the GSPI controller data after resource allocation. This will ensure that any early BAR cached by the GSPI controller driver is cleared. This will allow using GSPI before and after resource allocation in ramstage.
BUG=b:154333137 TEST=Ensure that the device boots to OS. Ensure that the TPM initialization is successful before and after resource allocation stage in ramstage.
Change-Id: I4444266e35cca54e2c9bd9221733e59737ad8ebd Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com --- M src/soc/intel/common/block/gspi/gspi.c 1 file changed, 7 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/44275/2
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44275 )
Change subject: soc/intel/common/block/gspi: Clear the GSPI controller data ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44275/1/src/soc/intel/common/block/... File src/soc/intel/common/block/gspi/gspi.c:
https://review.coreboot.org/c/coreboot/+/44275/1/src/soc/intel/common/block/... PS1, Line 732: memset(gspi_base, 0, sizeof(gspi_base));
please, no spaces at the start of a line
Done.
Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44275 )
Change subject: soc/intel/common/block/gspi: Clear the GSPI controller data ......................................................................
Patch Set 2: Code-Review+2
Karthik Ramasubramanian has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/44275 )
Change subject: soc/intel/common/block/gspi: Clear the GSPI controller data ......................................................................
Abandoned
Abandoning this CL in favor of CB:44084. Sorry for the inconvenience.
-
build bot (Jenkins) (Code Review) -
Edward O'Callaghan (Code Review)
-
Karthik Ramasubramanian (Code Review)