Attention is currently required from: Marc Jones, Anjaneya "Reddy" Chagam, Johnny Lin, Tim Wawrzynczak, Christian Walter, Angel Pons, Arthur Heymans, Nick Vaccaro, Michael Niewöhner, Patrick Rudolph, EricR Lai, Tim Chu.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61652 )
Change subject: soc/intel/xeon_sp: Add function to clear PMCON status bits
......................................................................
Patch Set 5:
(1 comment)
Patchset:
PS5:
I think you could move this to common and just split it between
CONFIG(SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE) and the inverse, something like
void pmc_clear_pmcon_sts(void)
{
if (!CONFIG(SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE)) {
uint32_t reg_val;
uint8_t *addr;
addr = pmc_mmio_regs();
reg_val = read32(addr + GEN_PMCON_A);
/* Clear SUS_PWR_FLR, GBL_RST_STS, HOST_RST_STS, PWR_FLR bits
* while retaining MS4V write-1-to-clear bit */
reg_val &= ~(MS4V);
write32((addr + GEN_PMCON_A), reg_val);
} else {
uint32_t reg_val;
const pci_devfn_t dev = PCH_DEV_PMC;
reg_val = pci_read_config32(dev, GEN_PMCON_A);
/*
* Clear SUS_PWR_FLR, GBL_RST_STS, HOST_RST_STS, PWR_FLR bits
* while retaining MS4V write-1-to-clear bit
*/
reg_val &= ~(MS4V);
pci_write_config32(dev, GEN_PMCON_A, reg_val)
}
}
Sure, this is still possible but before that we need to align DNV SoC as well.
Let me see if I get sometime this week to handle this. Looks like @Michael also shared the same concern.
@Tim, Do you agree if I pick this up after the current patch train gets in? Looks like this is nicely positioned and +2'ed ? Looking for your sugegstion.
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