Change in coreboot[master]: soc/intel/jasperlake: Add support for PCIe root port LTR configuration

[Aamir Bohra (Code Review)]

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43609 )

Change subject: soc/intel/jasperlake: Add support for PCIe root port LTR configuration
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soc/intel/jasperlake: Add support for PCIe root port LTR configuration

Signed-off-by: Aamir Bohra 
Change-Id: Iafe04c6e2434e23ceb9897fa62ac0defd4744772
---
M src/soc/intel/jasperlake/chip.h
M src/soc/intel/jasperlake/fsp_params.c
2 files changed, 7 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/43609/1

diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h
index d8ea560..1070ada 100644
--- a/src/soc/intel/jasperlake/chip.h
+++ b/src/soc/intel/jasperlake/chip.h
@@ -115,6 +115,9 @@
    /* Probe CLKREQ# signal before enabling CLKREQ# based power management.*/
    uint8_t PcieRpClkReqDetect[CONFIG_MAX_ROOT_PORTS];

+	/* Enable latency tolerance reporting Mechanism */
+	uint8_t PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS];
+
    /* PCIe RP L1 substate */
    enum L1_substates_control {
    	L1_SS_FSP_DEFAULT,
diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c
index 6493fd5..df24e58 100644
--- a/src/soc/intel/jasperlake/fsp_params.c
+++ b/src/soc/intel/jasperlake/fsp_params.c
@@ -133,6 +133,10 @@
    memcpy(params->PcieRpClkReqDetect, config->PcieRpClkReqDetect,
    	sizeof(config->PcieRpClkReqDetect));

+	/* Enable LTR support */
+	memcpy(params->PcieRpLtrEnable, config->PcieRpLtrEnable,
+		sizeof(config->PcieRpLtrEnable));
+
    /* USB configuration */
    for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {

[Aamir Bohra (Code Review)]

Aamir Bohra has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/43609 )

Change subject: soc/intel/jasperlake: Add support for PCIe root port LTR configuration
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Abandoned

Not required