Change in coreboot[master]: soc/mediatek/mt8183: Force DRAM retraining if hotkey pressed
Yu-Ping Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36090 )
Change subject: soc/mediatek/mt8183: Force DRAM retraining if hotkey pressed ......................................................................
soc/mediatek/mt8183: Force DRAM retraining if hotkey pressed
Similar to MRC cache on x86 platforms, when a hotkey is pressed during boot, the calibration data cache saved in the flash will be cleared, consequently triggering DRAM retraining (full calibration) in the next boot.
BRANCH=kukui BUG=b:139099592 TEST=emerge-kukui coreboot
Change-Id: I2f9225f359e1fe5733e8e1c48b396aaeeb9a58ab Signed-off-by: Yu-Ping Wu yupingso@chromium.org --- M src/soc/mediatek/mt8183/memory.c 1 file changed, 10 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/36090/1
diff --git a/src/soc/mediatek/mt8183/memory.c b/src/soc/mediatek/mt8183/memory.c index 5c10f49..5aa42c6 100644 --- a/src/soc/mediatek/mt8183/memory.c +++ b/src/soc/mediatek/mt8183/memory.c @@ -14,6 +14,7 @@ */
#include <assert.h> +#include <bootmode.h> #include <cbfs.h> #include <console/console.h> #include <ip_checksum.h> @@ -21,6 +22,7 @@ #include <soc/dramc_param.h> #include <soc/dramc_pi_api.h> #include <soc/emi.h> +#include <string.h> #include <symbols.h>
static int mt_mem_test(void) @@ -165,6 +167,14 @@ config |= DRAMC_CONFIG_EMCP;
const bool recovery_mode = vboot_recovery_mode_enabled(); + const bool force_retrain = get_recovery_mode_retrain_switch(); + + /* Clean flash to force retrain on next boot */ + if (recovery_mode && force_retrain) { + printk(BIOS_INFO, "Cleaning calibration data in flash\n"); + memset(dparam, 0, sizeof(*dparam)); + dparam_ops->write_to_flash(dparam); + }
/* Load calibration params from flash and run fast calibration */ if (!recovery_mode) {
Hello Nicolas Boichat, Julius Werner, Hung-Te Lin,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36090
to look at the new patch set (#2).
Change subject: soc/mediatek/mt8183: Force DRAM retraining if hotkey pressed ......................................................................
soc/mediatek/mt8183: Force DRAM retraining if hotkey pressed
Similar to MRC cache on x86 platforms, when a hotkey is pressed during boot, the calibration data cache saved in the flash will be cleared, consequently triggering DRAM retraining (full calibration) in the next boot.
BRANCH=kukui BUG=b:139099592 TEST=emerge-kukui coreboot
Change-Id: I2f9225f359e1fe5733e8e1c48b396aaeeb9a58ab Signed-off-by: Yu-Ping Wu yupingso@chromium.org --- M src/soc/mediatek/mt8183/memory.c 1 file changed, 10 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/36090/2
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36090 )
Change subject: soc/mediatek/mt8183: Force DRAM retraining if hotkey pressed ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/36090/2/src/soc/mediatek/mt8183/mem... File src/soc/mediatek/mt8183/memory.c:
https://review.coreboot.org/c/coreboot/+/36090/2/src/soc/mediatek/mt8183/mem... PS2, Line 170: const bool force_retrain = get_recovery_mode_retrain_switch(); again, the chromeos/vboot specific logic should live only in mainboard/romstage.c, and passed here.
(or, we can also wipe cache there).
https://review.coreboot.org/c/coreboot/+/36090/2/src/soc/mediatek/mt8183/mem... PS2, Line 175: 0 0xff
Hung-Te Lin has uploaded a new patch set (#3) to the change originally created by Yu-Ping Wu. ( https://review.coreboot.org/c/coreboot/+/36090 )
Change subject: mb/google/kukui: Force DRAM retraining if hotkey pressed ......................................................................
mb/google/kukui: Force DRAM retraining if hotkey pressed
Similar to MRC cache on x86 platforms, when a hotkey is pressed during boot, the calibration data cache saved in the flash will be cleared, consequently triggering DRAM retraining (full calibration) in the next boot.
BRANCH=kukui BUG=b:139099592 TEST=emerge-kukui coreboot
Change-Id: I2f9225f359e1fe5733e8e1c48b396aaeeb9a58ab Signed-off-by: Yu-Ping Wu yupingso@chromium.org --- M src/mainboard/google/kukui/romstage.c 1 file changed, 7 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/36090/3
Hung-Te Lin has uploaded a new patch set (#4) to the change originally created by Yu-Ping Wu. ( https://review.coreboot.org/c/coreboot/+/36090 )
Change subject: mb/google/kukui: Force DRAM retraining if hotkey pressed ......................................................................
mb/google/kukui: Force DRAM retraining if hotkey pressed
Similar to MRC cache on x86 platforms, when a hotkey is pressed during boot, the calibration data cache saved in the flash will be cleared, consequently triggering DRAM retraining (full calibration) in the next boot.
BRANCH=kukui BUG=b:139099592 TEST=emerge-kukui coreboot
Change-Id: I2f9225f359e1fe5733e8e1c48b396aaeeb9a58ab Signed-off-by: Yu-Ping Wu yupingso@chromium.org --- M src/mainboard/google/kukui/romstage.c 1 file changed, 7 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/36090/4
Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36090 )
Change subject: mb/google/kukui: Force DRAM retraining if hotkey pressed ......................................................................
Patch Set 5: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/36090/5/src/mainboard/google/kukui/... File src/mainboard/google/kukui/romstage.c:
https://review.coreboot.org/c/coreboot/+/36090/5/src/mainboard/google/kukui/... PS5, Line 79: if (recovery_mode && vboot_recovery_mode_memory_retrain()) { Maybe it would be better to put all this recovery-mode handling stuff directly into the SoC code? I don't see anything mainboard-specific here, and I don't see why other mainboards would want to interpret it differently.
(There's no rule that you're not allowed to have SoC code referencing vboot stuff, it's considered a core coreboot feature now. The x86 code does it all the time... e.g. see src/soc/intel/broadwell/romstage/raminit.c.)
Hung-Te Lin has uploaded a new patch set (#6) to the change originally created by Yu-Ping Wu. ( https://review.coreboot.org/c/coreboot/+/36090 )
Change subject: soc/mediatek/mt8183: Force DRAM retraining if hotkey pressed ......................................................................
soc/mediatek/mt8183: Force DRAM retraining if hotkey pressed
Similar to MRC cache on x86 platforms, when a hotkey is pressed during boot, the calibration data cache saved in the flash will be cleared, consequently triggering DRAM retraining (full calibration) in the next boot.
BRANCH=kukui BUG=b:139099592 TEST=emerge-kukui coreboot
Change-Id: I2f9225f359e1fe5733e8e1c48b396aaeeb9a58ab Signed-off-by: Yu-Ping Wu yupingso@chromium.org --- M src/soc/mediatek/mt8183/memory.c 1 file changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/36090/6
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36090 )
Change subject: soc/mediatek/mt8183: Force DRAM retraining if hotkey pressed ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36090/5/src/mainboard/google/kukui/... File src/mainboard/google/kukui/romstage.c:
https://review.coreboot.org/c/coreboot/+/36090/5/src/mainboard/google/kukui/... PS5, Line 79: if (recovery_mode && vboot_recovery_mode_memory_retrain()) {
Maybe it would be better to put all this recovery-mode handling stuff directly into the SoC code? I […]
I was considering that vboot stuff is not available on all systems, so we should try to not make SOC logic based on it (even if the functions provide dummy implementations); instead the SOC functions should provide ways to control the logic properly (for example should we do fast k or full k) and then let board use it own way overriding that (where vboot is the right choice for chrome devices, and other device may have their own preference)
But considering we also don't see that need now, and if more people feeling have these stuff directly in SOC folder is also making lots of sense, I'm fine with changing the design.
Hello Nicolas Boichat, Julius Werner, Hung-Te Lin, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36090
to look at the new patch set (#7).
Change subject: soc/mediatek/mt8183: Force DRAM retraining if hotkey pressed ......................................................................
soc/mediatek/mt8183: Force DRAM retraining if hotkey pressed
Similar to MRC cache on x86 platforms, when a hotkey is pressed during boot, the calibration data cache saved in the flash will be cleared, consequently triggering DRAM retraining (full calibration) in the next boot.
BRANCH=kukui BUG=b:139099592 TEST=emerge-kukui coreboot
Change-Id: I2f9225f359e1fe5733e8e1c48b396aaeeb9a58ab Signed-off-by: Yu-Ping Wu yupingso@chromium.org --- M src/soc/mediatek/mt8183/memory.c 1 file changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/36090/7
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36090 )
Change subject: soc/mediatek/mt8183: Force DRAM retraining if hotkey pressed ......................................................................
Patch Set 7: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/36090 )
Change subject: soc/mediatek/mt8183: Force DRAM retraining if hotkey pressed ......................................................................
soc/mediatek/mt8183: Force DRAM retraining if hotkey pressed
Similar to MRC cache on x86 platforms, when a hotkey is pressed during boot, the calibration data cache saved in the flash will be cleared, consequently triggering DRAM retraining (full calibration) in the next boot.
BRANCH=kukui BUG=b:139099592 TEST=emerge-kukui coreboot
Change-Id: I2f9225f359e1fe5733e8e1c48b396aaeeb9a58ab Signed-off-by: Yu-Ping Wu yupingso@chromium.org Reviewed-on: https://review.coreboot.org/c/coreboot/+/36090 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Hung-Te Lin hungte@chromium.org --- M src/soc/mediatek/mt8183/memory.c 1 file changed, 6 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Hung-Te Lin: Looks good to me, approved
diff --git a/src/soc/mediatek/mt8183/memory.c b/src/soc/mediatek/mt8183/memory.c index 2e63913..2a4ebbd 100644 --- a/src/soc/mediatek/mt8183/memory.c +++ b/src/soc/mediatek/mt8183/memory.c @@ -169,6 +169,12 @@ /* Load calibration params from flash and run fast calibration */ if (recovery_mode) { printk(BIOS_WARNING, "Skip loading cached calibration data\n"); + if (vboot_recovery_mode_memory_retrain()) { + printk(BIOS_WARNING, "Retrain memory in next boot\n"); + /* Use 0xFF as erased flash data. */ + memset(dparam, 0xff, sizeof(*dparam)); + dparam_ops->write_to_flash(dparam); + } } else if (dparam_ops->read_from_flash(dparam)) { printk(BIOS_INFO, "DRAM-K: Fast Calibration\n"); if (dram_run_fast_calibration(dparam, config) == 0) {
-
Hung-Te Lin (Code Review) -
Julius Werner (Code Review)
-
Patrick Georgi (Code Review)
-
Yu-Ping Wu (Code Review)