Change in coreboot[master]: soc/intel/cmn/pch/lockdown: Perform additional SPI lock configuration

[Subrata Banik (Code Review)]

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Arthur Heymans.
Hello build bot (Jenkins), Tim Wawrzynczak, Angel Pons, Arthur Heymans, Lean Sheng Tan, Eric Lai, Werner Zeh,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/63627

to look at the new patch set (#10).

Change subject: soc/intel/cmn/pch/lockdown: Perform additional SPI lock configuration
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soc/intel/cmn/pch/lockdown: Perform additional SPI lock configuration

This patch performs additional SPI lock configuration as per Intel
Flash Security Specification.

BUG=b:211954778
TEST=Able to build google/brya and verified all flash security
recommendations are being met.

Signed-off-by: Subrata Banik 
Change-Id: I922db8b46ac0d0523b91fc5aced88e38c8d8a560
---
M src/soc/intel/common/pch/lockdown/lockdown.c
1 file changed, 9 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/63627/10