Kyösti Mälkki (kyosti.malkki@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8538
-gerrit
commit 4632ba650ed608d8052a6bc0909b5c269e741435 Author: Kyösti Mälkki kyosti.malkki@gmail.com Date: Mon Feb 23 13:22:58 2015 +0200
AMD K8 fam10 : squashed buildtest [NOTFORMERGE]
Change-Id: I7270711f05f90e9dc403f0e013a38d852d1b6efd Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- src/arch/x86/include/arch/io.h | 2 +- src/device/Kconfig | 4 - src/device/device_util.c | 28 - src/device/hypertransport.c | 45 +- src/device/pci_device.c | 5 - src/include/device/device.h | 3 + src/include/device/hypertransport.h | 10 +- src/mainboard/advansus/a785e-i/Kconfig | 5 - src/mainboard/amd/bimini_fam10/Kconfig | 5 - src/mainboard/amd/dbm690t/Kconfig | 4 - src/mainboard/amd/mahogany/Kconfig | 4 - src/mainboard/amd/mahogany_fam10/Kconfig | 5 - src/mainboard/amd/pistachio/Kconfig | 4 - src/mainboard/amd/serengeti_cheetah/Kconfig | 5 +- src/mainboard/amd/serengeti_cheetah_fam10/Kconfig | 6 +- src/mainboard/amd/tilapia_fam10/Kconfig | 5 - src/mainboard/arima/hdama/Kconfig | 4 - src/mainboard/asrock/939a785gmh/Kconfig | 4 - src/mainboard/asus/a8n_e/Kconfig | 5 +- src/mainboard/asus/a8v-e_deluxe/Kconfig | 4 - src/mainboard/asus/a8v-e_se/Kconfig | 4 - src/mainboard/asus/k8v-x/Kconfig | 4 - src/mainboard/asus/kfsn4-dre/Kconfig | 5 - src/mainboard/asus/m2n-e/Kconfig | 5 +- src/mainboard/asus/m2v-mx_se/Kconfig | 4 - src/mainboard/asus/m2v/Kconfig | 4 - src/mainboard/asus/m4a78-em/Kconfig | 5 - src/mainboard/asus/m4a785-m/Kconfig | 5 - src/mainboard/asus/m4a785t-m/Kconfig | 5 - src/mainboard/asus/m5a88-v/Kconfig | 5 - src/mainboard/avalue/eax-785e/Kconfig | 5 - src/mainboard/broadcom/blast/Kconfig | 4 - src/mainboard/gigabyte/ga_2761gxdk/Kconfig | 5 +- src/mainboard/gigabyte/m57sli/Kconfig | 5 +- src/mainboard/gigabyte/ma785gm/Kconfig | 5 - src/mainboard/gigabyte/ma785gmt/Kconfig | 5 - src/mainboard/gigabyte/ma78gm/Kconfig | 5 - src/mainboard/hp/dl145_g1/Kconfig | 5 +- src/mainboard/hp/dl145_g3/Kconfig | 5 +- src/mainboard/hp/dl165_g6_fam10/Kconfig | 6 +- src/mainboard/ibm/e325/Kconfig | 4 - src/mainboard/ibm/e326/Kconfig | 4 - src/mainboard/iei/kino-780am2-fam10/Kconfig | 5 - src/mainboard/iwill/dk8_htx/Kconfig | 5 +- src/mainboard/iwill/dk8s2/Kconfig | 4 - src/mainboard/iwill/dk8x/Kconfig | 4 - src/mainboard/jetway/pa78vm5/Kconfig | 5 - src/mainboard/kontron/kt690/Kconfig | 4 - src/mainboard/msi/ms7135/Kconfig | 5 +- src/mainboard/msi/ms7260/Kconfig | 5 +- src/mainboard/msi/ms9185/Kconfig | 5 +- src/mainboard/msi/ms9282/Kconfig | 4 - src/mainboard/msi/ms9652_fam10/Kconfig | 5 - src/mainboard/newisys/khepri/Kconfig | 4 - src/mainboard/nvidia/l1_2pvv/Kconfig | 5 +- src/mainboard/siemens/sitemp_g1p1/Kconfig | 4 - src/mainboard/sunw/ultra40/Kconfig | 5 +- src/mainboard/supermicro/h8dme/Kconfig | 5 +- src/mainboard/supermicro/h8dmr/Kconfig | 5 +- src/mainboard/supermicro/h8dmr_fam10/Kconfig | 6 +- src/mainboard/supermicro/h8qme_fam10/Kconfig | 6 +- src/mainboard/supermicro/h8scm_fam10/Kconfig | 5 - src/mainboard/technexion/tim5690/Kconfig | 4 - src/mainboard/technexion/tim8690/Kconfig | 4 - src/mainboard/tyan/s2850/Kconfig | 4 - src/mainboard/tyan/s2875/Kconfig | 4 - src/mainboard/tyan/s2880/Kconfig | 4 - src/mainboard/tyan/s2881/Kconfig | 5 +- src/mainboard/tyan/s2882/Kconfig | 4 - src/mainboard/tyan/s2885/Kconfig | 5 +- src/mainboard/tyan/s2891/Kconfig | 5 +- src/mainboard/tyan/s2892/Kconfig | 5 +- src/mainboard/tyan/s2895/Kconfig | 5 +- src/mainboard/tyan/s2912/Kconfig | 5 +- src/mainboard/tyan/s2912_fam10/Kconfig | 6 +- src/mainboard/tyan/s4880/Kconfig | 4 - src/mainboard/tyan/s4882/Kconfig | 4 - src/mainboard/winent/mb6047/Kconfig | 5 +- src/northbridge/amd/amdfam10/Kconfig | 7 +- src/northbridge/amd/amdfam10/Makefile.inc | 1 + src/northbridge/amd/amdfam10/amdfam10.h | 135 +---- src/northbridge/amd/amdfam10/conf.c | 612 ---------------------- src/northbridge/amd/amdfam10/debug.c | 4 - src/northbridge/amd/amdfam10/ht_config.c | 236 +++++++++ src/northbridge/amd/amdfam10/ht_config.h | 55 ++ src/northbridge/amd/amdfam10/northbridge.c | 378 ++++--------- src/northbridge/amd/amdk8/Kconfig | 3 + src/northbridge/amd/amdk8/northbridge.c | 214 ++++---- 88 files changed, 599 insertions(+), 1476 deletions(-)
diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h index 9987578..3130f64 100644 --- a/src/arch/x86/include/arch/io.h +++ b/src/arch/x86/include/arch/io.h @@ -267,7 +267,7 @@ static inline pci_devfn_t pci_io_locate_device(unsigned pci_id, pci_devfn_t dev)
static inline pci_devfn_t pci_locate_device(unsigned pci_id, pci_devfn_t dev) { - for(; dev <= PCI_DEV(255|(((1<<CONFIG_PCI_BUS_SEGN_BITS)-1)<<8), 31, 7); dev += PCI_DEV(0,0,1)) { + for(; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0,0,1)) { unsigned int id; id = pci_read_config32(dev, 0); if (id == pci_id) { diff --git a/src/device/Kconfig b/src/device/Kconfig index 91da02a..03b98a1 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -251,10 +251,6 @@ config PCIEXP_ASPM help Detect and enable ASPM on PCIe links.
-config PCI_BUS_SEGN_BITS - int - default 0 - config EARLY_PCI_BRIDGE bool "Early PCI bridge" depends on PCI diff --git a/src/device/device_util.c b/src/device/device_util.c index 62a815f..d970429 100644 --- a/src/device/device_util.c +++ b/src/device/device_util.c @@ -251,20 +251,11 @@ const char *dev_path(device_t dev) memcpy(buffer, "Root Device", 12); break; case DEVICE_PATH_PCI: -#if CONFIG_PCI_BUS_SEGN_BITS - snprintf(buffer, sizeof (buffer), - "PCI: %04x:%02x:%02x.%01x", - dev->bus->secondary >> 8, - dev->bus->secondary & 0xff, - PCI_SLOT(dev->path.pci.devfn), - PCI_FUNC(dev->path.pci.devfn)); -#else snprintf(buffer, sizeof (buffer), "PCI: %02x:%02x.%01x", dev->bus->secondary, PCI_SLOT(dev->path.pci.devfn), PCI_FUNC(dev->path.pci.devfn)); -#endif break; case DEVICE_PATH_PNP: snprintf(buffer, sizeof (buffer), "PNP: %04x.%01x", @@ -643,14 +634,8 @@ void report_resource_stored(device_t dev, struct resource *resource, buf[0] = '\0';
if (resource->flags & IORESOURCE_PCI_BRIDGE) { -#if CONFIG_PCI_BUS_SEGN_BITS - snprintf(buf, sizeof (buf), - "bus %04x:%02x ", dev->bus->secondary >> 8, - dev->link_list->secondary & 0xff); -#else snprintf(buf, sizeof (buf), "bus %02x ", dev->link_list->secondary); -#endif } printk(BIOS_DEBUG, "%s %02lx <- [0x%010llx - 0x%010llx] size 0x%08llx " "gran 0x%02x %s%s%s\n", dev_path(dev), resource->index, @@ -855,19 +840,6 @@ void show_one_resource(int debug_level, struct device *dev, end = resource_end(resource); buf[0] = '\0';
-/* - if (resource->flags & IORESOURCE_BRIDGE) { -#if CONFIG_PCI_BUS_SEGN_BITS - snprintf(buf, sizeof (buf), "bus %04x:%02x ", - dev->bus->secondary >> 8, - dev->link[0].secondary & 0xff); -#else - snprintf(buf, sizeof (buf), - "bus %02x ", dev->link[0].secondary); -#endif - } -*/ - do_printk(debug_level, "%s %02lx <- [0x%010llx - 0x%010llx] " "size 0x%08llx gran 0x%02x %s%s%s\n", dev_path(dev), resource->index, base, end, resource->size, resource->gran, diff --git a/src/device/hypertransport.c b/src/device/hypertransport.c index d27e66b..ec0601b 100644 --- a/src/device/hypertransport.c +++ b/src/device/hypertransport.c @@ -248,7 +248,7 @@ static void ht_collapse_early_enumeration(struct bus *bus, } }
-unsigned int hypertransport_scan_chain(struct bus *bus, unsigned min_devfn, +static unsigned int do_hypertransport_scan_chain(struct bus *bus, unsigned min_devfn, unsigned max_devfn, unsigned int max, unsigned *ht_unitid_base, unsigned offset_unitid) @@ -479,6 +479,30 @@ end_of_chain: return max; }
+unsigned int hypertransport_scan_chain(struct bus *bus, unsigned int max) +{ + int i; + unsigned int max_devfn; + u32 ht_unitid_base[4]; + + for (i = 0; i < 4; i++) + ht_unitid_base[i] = 0x20; + + if (bus->secondary == 0) + max_devfn = (CONFIG_CDB << 3) - 1; + else + max_devfn = (0x20 << 3) - 1; + + max = do_hypertransport_scan_chain(bus, 0, max_devfn, max, + ht_unitid_base, offset_unit_id(bus->secondary == 0)); + + bus->hcdn_reg = 0; + for (i = 0; i < 4; i++) + bus->hcdn_reg |= (ht_unitid_base[i] & 0xff) << (i*8); + + return max; +} + /** * Scan a PCI bridge and the buses behind the bridge. * @@ -498,7 +522,7 @@ static unsigned int hypertransport_scan_chain_x(struct bus *bus, { unsigned int ht_unitid_base[4]; unsigned int offset_unitid = 1; - return hypertransport_scan_chain(bus, min_devfn, max_devfn, max, + return do_hypertransport_scan_chain(bus, min_devfn, max_devfn, max, ht_unitid_base, offset_unitid); }
@@ -507,6 +531,23 @@ unsigned int ht_scan_bridge(struct device *dev, unsigned int max) return do_pci_scan_bridge(dev, max, hypertransport_scan_chain_x); }
+bool ht_is_non_coherent_link(struct bus *link) +{ + u32 link_type; + do { + link_type = pci_read_config32(link->dev, link->cap + 0x18); + } while (link_type & ConnectionPending); + + if (!(link_type & LinkConnected)) + return false; + + do { + link_type = pci_read_config32(link->dev, link->cap + 0x18); + } while (!(link_type & InitComplete)); + + return !!(link_type & NonCoherent); +} + /** Default device operations for hypertransport bridges */ static struct pci_operations ht_bus_ops_pci = { .set_subsystem = 0, diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 538ab4c..6cb99bf 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -1090,12 +1090,7 @@ unsigned int pci_scan_bus(struct bus *bus, unsigned min_devfn, struct device *old_devices; struct device *child;
-#if CONFIG_PCI_BUS_SEGN_BITS - printk(BIOS_DEBUG, "PCI: pci_scan_bus for bus %04x:%02x\n", - bus->secondary >> 8, bus->secondary & 0xff); -#else printk(BIOS_DEBUG, "PCI: pci_scan_bus for bus %02x\n", bus->secondary); -#endif
/* Maximum sane devfn is 0xFF. */ if (max_devfn > 0xff) { diff --git a/src/include/device/device.h b/src/include/device/device.h index 436420f..d626165 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -86,8 +86,11 @@ struct bus { uint16_t secondary; /* secondary bus number */ uint16_t subordinate; /* max subordinate bus number */ unsigned char cap; /* PCi capability offset */ + uint32_t hcdn_reg; /* For HyperTransport link */ + unsigned reset_needed : 1; unsigned disable_relaxed_ordering : 1; + unsigned ht_link_up : 1; };
/* diff --git a/src/include/device/hypertransport.h b/src/include/device/hypertransport.h index e927d61..6034b27 100644 --- a/src/include/device/hypertransport.h +++ b/src/include/device/hypertransport.h @@ -3,8 +3,14 @@
#include <device/hypertransport_def.h>
-unsigned int hypertransport_scan_chain(struct bus *bus, - unsigned min_devfn, unsigned max_devfn, unsigned int max, unsigned *ht_unit_base, unsigned offset_unitid); +/* FIXME */ +#define LinkConnected (1 << 0) +#define InitComplete (1 << 1) +#define NonCoherent (1 << 2) +#define ConnectionPending (1 << 4) +bool ht_is_non_coherent_link(struct bus *link); + +unsigned int hypertransport_scan_chain(struct bus *bus, unsigned int max); unsigned int ht_scan_bridge(struct device *dev, unsigned int max); extern struct device_operations default_ht_ops_bus;
diff --git a/src/mainboard/advansus/a785e-i/Kconfig b/src/mainboard/advansus/a785e-i/Kconfig index ab77898..c84bf4d 100644 --- a/src/mainboard/advansus/a785e-i/Kconfig +++ b/src/mainboard/advansus/a785e-i/Kconfig @@ -16,7 +16,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID - select AMDMCT select HAVE_MP_TABLE select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_1024 @@ -53,10 +52,6 @@ config HW_MEM_HOLE_SIZE_AUTO_INC bool default n
-config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/amd/bimini_fam10/Kconfig b/src/mainboard/amd/bimini_fam10/Kconfig index 1af8d64..261c60a 100644 --- a/src/mainboard/amd/bimini_fam10/Kconfig +++ b/src/mainboard/amd/bimini_fam10/Kconfig @@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_TABLES select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID - select AMDMCT select BOARD_ROMSIZE_KB_2048 select ENABLE_APIC_EXT_ID select GFXUMA @@ -53,10 +52,6 @@ config HW_MEM_HOLE_SIZE_AUTO_INC bool default n
-config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/amd/dbm690t/Kconfig b/src/mainboard/amd/dbm690t/Kconfig index 70d63ad..77bafc5 100644 --- a/src/mainboard/amd/dbm690t/Kconfig +++ b/src/mainboard/amd/dbm690t/Kconfig @@ -36,10 +36,6 @@ config MAX_PHYSICAL_CPUS int default 1
-config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/amd/mahogany/Kconfig b/src/mainboard/amd/mahogany/Kconfig index 394ad77..8861b4a 100644 --- a/src/mainboard/amd/mahogany/Kconfig +++ b/src/mainboard/amd/mahogany/Kconfig @@ -47,10 +47,6 @@ config MAX_PHYSICAL_CPUS int default 2
-config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/amd/mahogany_fam10/Kconfig b/src/mainboard/amd/mahogany_fam10/Kconfig index acf88ef..393882c 100644 --- a/src/mainboard/amd/mahogany_fam10/Kconfig +++ b/src/mainboard/amd/mahogany_fam10/Kconfig @@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_MP_TABLE select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID - select AMDMCT select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_1024 select ENABLE_APIC_EXT_ID @@ -41,10 +40,6 @@ config MAX_PHYSICAL_CPUS int default 2
-config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/amd/pistachio/Kconfig b/src/mainboard/amd/pistachio/Kconfig index 9a91eec..2296e82 100644 --- a/src/mainboard/amd/pistachio/Kconfig +++ b/src/mainboard/amd/pistachio/Kconfig @@ -44,10 +44,6 @@ config MAX_PHYSICAL_CPUS int default 1
-config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/amd/serengeti_cheetah/Kconfig b/src/mainboard/amd/serengeti_cheetah/Kconfig index e1363eb..2d2d4d1 100644 --- a/src/mainboard/amd/serengeti_cheetah/Kconfig +++ b/src/mainboard/amd/serengeti_cheetah/Kconfig @@ -10,6 +10,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_AMD_AMD8111 select SOUTHBRIDGE_AMD_AMD8131 + select HT_CHAIN_DISTRIBUTE select SUPERIO_WINBOND_W83627HF select PARALLEL_CPU_INIT select HAVE_OPTION_TABLE @@ -55,10 +56,6 @@ config MEM_TRAIN_SEQ int default 1
-config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config HT_CHAIN_END_UNITID_BASE hex default 0x6 diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig b/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig index 74f3c3b..3e6e025 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig +++ b/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig @@ -8,12 +8,12 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDFAM10 select SOUTHBRIDGE_AMD_AMD8111 select SOUTHBRIDGE_AMD_AMD8132 + select HT_CHAIN_DISTRIBUTE select SUPERIO_WINBOND_W83627HF select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select SB_HT_CHAIN_UNITID_OFFSET_ONLY - select AMDMCT select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_1024 select ENABLE_APIC_EXT_ID @@ -42,10 +42,6 @@ config MAX_PHYSICAL_CPUS int default 8
-config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config HT_CHAIN_END_UNITID_BASE hex default 0x6 diff --git a/src/mainboard/amd/tilapia_fam10/Kconfig b/src/mainboard/amd/tilapia_fam10/Kconfig index b6c9448..491a886 100644 --- a/src/mainboard/amd/tilapia_fam10/Kconfig +++ b/src/mainboard/amd/tilapia_fam10/Kconfig @@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_MP_TABLE select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID - select AMDMCT select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_1024 select ENABLE_APIC_EXT_ID @@ -41,10 +40,6 @@ config MAX_PHYSICAL_CPUS int default 2
-config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/arima/hdama/Kconfig b/src/mainboard/arima/hdama/Kconfig index 49860b3..66177f5 100644 --- a/src/mainboard/arima/hdama/Kconfig +++ b/src/mainboard/arima/hdama/Kconfig @@ -38,10 +38,6 @@ config MAX_PHYSICAL_CPUS int default 2
-config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x20 diff --git a/src/mainboard/asrock/939a785gmh/Kconfig b/src/mainboard/asrock/939a785gmh/Kconfig index cfaa599..2148385 100644 --- a/src/mainboard/asrock/939a785gmh/Kconfig +++ b/src/mainboard/asrock/939a785gmh/Kconfig @@ -49,10 +49,6 @@ config MAX_PHYSICAL_CPUS int default 2
-config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/asus/a8n_e/Kconfig b/src/mainboard/asus/a8n_e/Kconfig index 5b7c1e6..1852ae4 100644 --- a/src/mainboard/asus/a8n_e/Kconfig +++ b/src/mainboard/asus/a8n_e/Kconfig @@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select CPU_AMD_SOCKET_939 select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_CK804 + select HT_CHAIN_DISTRIBUTE select SUPERIO_ITE_IT8712F select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT @@ -54,10 +55,6 @@ config HT_CHAIN_UNITID_BASE hex default 0x0
-config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config IRQ_SLOT_COUNT int default 13 diff --git a/src/mainboard/asus/a8v-e_deluxe/Kconfig b/src/mainboard/asus/a8v-e_deluxe/Kconfig index 8ebff31..a1c2fd9 100644 --- a/src/mainboard/asus/a8v-e_deluxe/Kconfig +++ b/src/mainboard/asus/a8v-e_deluxe/Kconfig @@ -33,10 +33,6 @@ config APIC_ID_OFFSET hex default 0x10
-config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config MAINBOARD_PART_NUMBER string default "A8V-E Deluxe" diff --git a/src/mainboard/asus/a8v-e_se/Kconfig b/src/mainboard/asus/a8v-e_se/Kconfig index d819b0d..dffe9eb 100644 --- a/src/mainboard/asus/a8v-e_se/Kconfig +++ b/src/mainboard/asus/a8v-e_se/Kconfig @@ -33,10 +33,6 @@ config APIC_ID_OFFSET hex default 0x10
-config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config MAINBOARD_PART_NUMBER string default "A8V-E SE" diff --git a/src/mainboard/asus/k8v-x/Kconfig b/src/mainboard/asus/k8v-x/Kconfig index 1deb5b6..52bf661 100644 --- a/src/mainboard/asus/k8v-x/Kconfig +++ b/src/mainboard/asus/k8v-x/Kconfig @@ -32,10 +32,6 @@ config APIC_ID_OFFSET hex default 0x10
-config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config MAINBOARD_PART_NUMBER string default "K8V-X" diff --git a/src/mainboard/asus/kfsn4-dre/Kconfig b/src/mainboard/asus/kfsn4-dre/Kconfig index 03f3b7c..39a6d43 100644 --- a/src/mainboard/asus/kfsn4-dre/Kconfig +++ b/src/mainboard/asus/kfsn4-dre/Kconfig @@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select LIFT_BSP_APIC_ID select BOARD_ROMSIZE_KB_1024 select ENABLE_APIC_EXT_ID - select AMDMCT select MMCONF_SUPPORT_DEFAULT select DRIVERS_I2C_W83793 select DRIVERS_XGI_Z9S @@ -41,10 +40,6 @@ config APIC_ID_OFFSET hex default 0
-config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config MAINBOARD_PART_NUMBER string default "KFSN4-DRE" diff --git a/src/mainboard/asus/m2n-e/Kconfig b/src/mainboard/asus/m2n-e/Kconfig index 7292bf3..448cd9f 100644 --- a/src/mainboard/asus/m2n-e/Kconfig +++ b/src/mainboard/asus/m2n-e/Kconfig @@ -26,6 +26,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DIMM_DDR2 select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_MCP55 + select HT_CHAIN_DISTRIBUTE select MCP55_USE_NIC select MCP55_USE_AZA select SUPERIO_ITE_IT8716F @@ -57,10 +58,6 @@ config MEM_TRAIN_SEQ int default 2
-config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config MAINBOARD_PART_NUMBER string default "M2N-E" diff --git a/src/mainboard/asus/m2v-mx_se/Kconfig b/src/mainboard/asus/m2v-mx_se/Kconfig index 27b8253..3b66235 100644 --- a/src/mainboard/asus/m2v-mx_se/Kconfig +++ b/src/mainboard/asus/m2v-mx_se/Kconfig @@ -67,10 +67,6 @@ config HT_CHAIN_UNITID_BASE hex default 0x0
-config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x20 diff --git a/src/mainboard/asus/m2v/Kconfig b/src/mainboard/asus/m2v/Kconfig index 35ad38d..72527be 100644 --- a/src/mainboard/asus/m2v/Kconfig +++ b/src/mainboard/asus/m2v/Kconfig @@ -36,10 +36,6 @@ config APIC_ID_OFFSET hex default 0x10
-config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config MAINBOARD_PART_NUMBER string default "M2V" diff --git a/src/mainboard/asus/m4a78-em/Kconfig b/src/mainboard/asus/m4a78-em/Kconfig index 6118d12..0382daf 100644 --- a/src/mainboard/asus/m4a78-em/Kconfig +++ b/src/mainboard/asus/m4a78-em/Kconfig @@ -13,7 +13,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_MP_TABLE select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID - select AMDMCT select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_1024 select ENABLE_APIC_EXT_ID @@ -40,10 +39,6 @@ config MAX_PHYSICAL_CPUS int default 2
-config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/asus/m4a785-m/Kconfig b/src/mainboard/asus/m4a785-m/Kconfig index a5c7631..a945d2a 100644 --- a/src/mainboard/asus/m4a785-m/Kconfig +++ b/src/mainboard/asus/m4a785-m/Kconfig @@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_MP_TABLE select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID - select AMDMCT select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_1024 select ENABLE_APIC_EXT_ID @@ -41,10 +40,6 @@ config MAX_PHYSICAL_CPUS int default 2
-config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/asus/m4a785t-m/Kconfig b/src/mainboard/asus/m4a785t-m/Kconfig index 19d8fd2..a347f02 100644 --- a/src/mainboard/asus/m4a785t-m/Kconfig +++ b/src/mainboard/asus/m4a785t-m/Kconfig @@ -16,7 +16,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_MP_TABLE select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID - select AMDMCT select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_1024 select ENABLE_APIC_EXT_ID @@ -43,10 +42,6 @@ config MAX_PHYSICAL_CPUS int default 2
-config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/asus/m5a88-v/Kconfig b/src/mainboard/asus/m5a88-v/Kconfig index 3a0f70f..8a8fcab 100644 --- a/src/mainboard/asus/m5a88-v/Kconfig +++ b/src/mainboard/asus/m5a88-v/Kconfig @@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID - select AMDMCT select HAVE_MP_TABLE select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_2048 @@ -51,10 +50,6 @@ config HW_MEM_HOLE_SIZE_AUTO_INC bool default n
-config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/avalue/eax-785e/Kconfig b/src/mainboard/avalue/eax-785e/Kconfig index 091dcee..24a5b07 100644 --- a/src/mainboard/avalue/eax-785e/Kconfig +++ b/src/mainboard/avalue/eax-785e/Kconfig @@ -16,7 +16,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID - select AMDMCT select HAVE_MP_TABLE select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_2048 @@ -53,10 +52,6 @@ config HW_MEM_HOLE_SIZE_AUTO_INC bool default n
-config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/broadcom/blast/Kconfig b/src/mainboard/broadcom/blast/Kconfig index b821f7a..ddd2aca 100644 --- a/src/mainboard/broadcom/blast/Kconfig +++ b/src/mainboard/broadcom/blast/Kconfig @@ -31,10 +31,6 @@ config APIC_ID_OFFSET hex default 0x0
-config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config MAINBOARD_PART_NUMBER string default "Blast" diff --git a/src/mainboard/gigabyte/ga_2761gxdk/Kconfig b/src/mainboard/gigabyte/ga_2761gxdk/Kconfig index a79c28f..e182c99 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/Kconfig +++ b/src/mainboard/gigabyte/ga_2761gxdk/Kconfig @@ -6,6 +6,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DIMM_DDR2 select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_SIS_SIS966 + select HT_CHAIN_DISTRIBUTE select SUPERIO_ITE_IT8716F select PARALLEL_CPU_INIT select HAVE_OPTION_TABLE @@ -37,10 +38,6 @@ config MEM_TRAIN_SEQ int default 2
-config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config MAINBOARD_PART_NUMBER string default "GA-2761GXDK" diff --git a/src/mainboard/gigabyte/m57sli/Kconfig b/src/mainboard/gigabyte/m57sli/Kconfig index 6ef94ce..cc8be43 100644 --- a/src/mainboard/gigabyte/m57sli/Kconfig +++ b/src/mainboard/gigabyte/m57sli/Kconfig @@ -6,6 +6,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DIMM_DDR2 select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_MCP55 + select HT_CHAIN_DISTRIBUTE select MCP55_USE_NIC select MCP55_USE_AZA select SUPERIO_ITE_IT8716F @@ -41,10 +42,6 @@ config MEM_TRAIN_SEQ int default 2
-config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config MAINBOARD_PART_NUMBER string default "GA-M57SLI-S4" diff --git a/src/mainboard/gigabyte/ma785gm/Kconfig b/src/mainboard/gigabyte/ma785gm/Kconfig index f830e81..bf441e9 100644 --- a/src/mainboard/gigabyte/ma785gm/Kconfig +++ b/src/mainboard/gigabyte/ma785gm/Kconfig @@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_MP_TABLE select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID - select AMDMCT select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_1024 select ENABLE_APIC_EXT_ID @@ -41,10 +40,6 @@ config MAX_PHYSICAL_CPUS int default 2
-config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/gigabyte/ma785gmt/Kconfig b/src/mainboard/gigabyte/ma785gmt/Kconfig index 505d033..827c8da 100644 --- a/src/mainboard/gigabyte/ma785gmt/Kconfig +++ b/src/mainboard/gigabyte/ma785gmt/Kconfig @@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_MP_TABLE select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID - select AMDMCT select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_1024 select ENABLE_APIC_EXT_ID @@ -41,10 +40,6 @@ config MAX_PHYSICAL_CPUS int default 2
-config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/gigabyte/ma78gm/Kconfig b/src/mainboard/gigabyte/ma78gm/Kconfig index b36640f..3d85708 100644 --- a/src/mainboard/gigabyte/ma78gm/Kconfig +++ b/src/mainboard/gigabyte/ma78gm/Kconfig @@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_MP_TABLE select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID - select AMDMCT select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_1024 select ENABLE_APIC_EXT_ID @@ -41,10 +40,6 @@ config MAX_PHYSICAL_CPUS int default 2
-config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/hp/dl145_g1/Kconfig b/src/mainboard/hp/dl145_g1/Kconfig index 0c6d642..74ce0e7 100644 --- a/src/mainboard/hp/dl145_g1/Kconfig +++ b/src/mainboard/hp/dl145_g1/Kconfig @@ -6,6 +6,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_AMD_AMD8131 select SOUTHBRIDGE_AMD_AMD8111 + select HT_CHAIN_DISTRIBUTE select SUPERIO_WINBOND_W83627HF select HAVE_HARD_RESET select HAVE_OPTION_TABLE @@ -28,10 +29,6 @@ config APIC_ID_OFFSET hex default 0x0
-config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config MAINBOARD_PART_NUMBER string default "ProLiant DL145 G1" diff --git a/src/mainboard/hp/dl145_g3/Kconfig b/src/mainboard/hp/dl145_g3/Kconfig index 439188a..da20fb3 100644 --- a/src/mainboard/hp/dl145_g3/Kconfig +++ b/src/mainboard/hp/dl145_g3/Kconfig @@ -8,6 +8,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_BROADCOM_BCM21000 select SOUTHBRIDGE_BROADCOM_BCM5785 + select HT_CHAIN_DISTRIBUTE select SUPERIO_SERVERENGINES_PILOT select SUPERIO_NSC_PC87417 select HAVE_OPTION_TABLE @@ -56,10 +57,6 @@ config HT_CHAIN_UNITID_BASE hex default 0x6
-config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config IRQ_SLOT_COUNT int default 15 diff --git a/src/mainboard/hp/dl165_g6_fam10/Kconfig b/src/mainboard/hp/dl165_g6_fam10/Kconfig index f6aea01..408fe66 100644 --- a/src/mainboard/hp/dl165_g6_fam10/Kconfig +++ b/src/mainboard/hp/dl165_g6_fam10/Kconfig @@ -6,6 +6,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDFAM10 select SOUTHBRIDGE_BROADCOM_BCM21000 select SOUTHBRIDGE_BROADCOM_BCM5785 + select HT_CHAIN_DISTRIBUTE select SUPERIO_SERVERENGINES_PILOT select SUPERIO_NSC_PC87417 select DIMM_DDR2 @@ -16,7 +17,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select LIFT_BSP_APIC_ID select BOARD_ROMSIZE_KB_1024 select ENABLE_APIC_EXT_ID - select AMDMCT select QRANK_DIMM_SUPPORT select MMCONF_SUPPORT_DEFAULT
@@ -56,10 +56,6 @@ config HT_CHAIN_UNITID_BASE hex default 0x6
-config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config IRQ_SLOT_COUNT int default 15 diff --git a/src/mainboard/ibm/e325/Kconfig b/src/mainboard/ibm/e325/Kconfig index 10b6fde..0400677 100644 --- a/src/mainboard/ibm/e325/Kconfig +++ b/src/mainboard/ibm/e325/Kconfig @@ -43,10 +43,6 @@ config MAX_PHYSICAL_CPUS int default 1
-config SB_HT_CHAIN_ON_BUS0 - int - default 0 - config HT_CHAIN_END_UNITID_BASE hex default 0x20 diff --git a/src/mainboard/ibm/e326/Kconfig b/src/mainboard/ibm/e326/Kconfig index 005012a..bd2bb26 100644 --- a/src/mainboard/ibm/e326/Kconfig +++ b/src/mainboard/ibm/e326/Kconfig @@ -43,10 +43,6 @@ config MAX_PHYSICAL_CPUS int default 2
-config SB_HT_CHAIN_ON_BUS0 - int - default 0 - config HT_CHAIN_END_UNITID_BASE hex default 0x20 diff --git a/src/mainboard/iei/kino-780am2-fam10/Kconfig b/src/mainboard/iei/kino-780am2-fam10/Kconfig index 069a4ae..4b3bce6 100644 --- a/src/mainboard/iei/kino-780am2-fam10/Kconfig +++ b/src/mainboard/iei/kino-780am2-fam10/Kconfig @@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_MP_TABLE select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID - select AMDMCT select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_1024 select ENABLE_APIC_EXT_ID @@ -41,10 +40,6 @@ config MAX_PHYSICAL_CPUS int default 2
-config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/iwill/dk8_htx/Kconfig b/src/mainboard/iwill/dk8_htx/Kconfig index cdfd99a..929f47f 100644 --- a/src/mainboard/iwill/dk8_htx/Kconfig +++ b/src/mainboard/iwill/dk8_htx/Kconfig @@ -6,6 +6,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_AMD_AMD8111 select SOUTHBRIDGE_AMD_AMD8131 + select HT_CHAIN_DISTRIBUTE select SUPERIO_WINBOND_W83627HF select PARALLEL_CPU_INIT select HAVE_OPTION_TABLE @@ -38,10 +39,6 @@ config MAX_PHYSICAL_CPUS int default 2
-config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config HT_CHAIN_END_UNITID_BASE hex default 0x6 diff --git a/src/mainboard/iwill/dk8s2/Kconfig b/src/mainboard/iwill/dk8s2/Kconfig index c4de3a1..6b54645 100644 --- a/src/mainboard/iwill/dk8s2/Kconfig +++ b/src/mainboard/iwill/dk8s2/Kconfig @@ -37,10 +37,6 @@ config MAX_PHYSICAL_CPUS int default 2
-config SB_HT_CHAIN_ON_BUS0 - int - default 0 - config HT_CHAIN_END_UNITID_BASE hex default 0x20 diff --git a/src/mainboard/iwill/dk8x/Kconfig b/src/mainboard/iwill/dk8x/Kconfig index af35bb6..f2660c6 100644 --- a/src/mainboard/iwill/dk8x/Kconfig +++ b/src/mainboard/iwill/dk8x/Kconfig @@ -36,10 +36,6 @@ config MAX_PHYSICAL_CPUS int default 2
-config SB_HT_CHAIN_ON_BUS0 - int - default 0 - config HT_CHAIN_END_UNITID_BASE hex default 0x20 diff --git a/src/mainboard/jetway/pa78vm5/Kconfig b/src/mainboard/jetway/pa78vm5/Kconfig index 56ad128..30478d2 100644 --- a/src/mainboard/jetway/pa78vm5/Kconfig +++ b/src/mainboard/jetway/pa78vm5/Kconfig @@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_MP_TABLE select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID - select AMDMCT select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_1024 select ENABLE_APIC_EXT_ID @@ -41,10 +40,6 @@ config MAX_PHYSICAL_CPUS int default 2
-config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/kontron/kt690/Kconfig b/src/mainboard/kontron/kt690/Kconfig index 8d1f039..e679e66 100644 --- a/src/mainboard/kontron/kt690/Kconfig +++ b/src/mainboard/kontron/kt690/Kconfig @@ -37,10 +37,6 @@ config MAX_PHYSICAL_CPUS int default 1
-config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/msi/ms7135/Kconfig b/src/mainboard/msi/ms7135/Kconfig index f2cfd9a..50f989e 100644 --- a/src/mainboard/msi/ms7135/Kconfig +++ b/src/mainboard/msi/ms7135/Kconfig @@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select CPU_AMD_SOCKET_754 select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_CK804 + select HT_CHAIN_DISTRIBUTE select SUPERIO_WINBOND_W83627THG select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE @@ -43,10 +44,6 @@ config HT_CHAIN_END_UNITID_BASE hex default 0x20
-config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config IRQ_SLOT_COUNT int default 13 diff --git a/src/mainboard/msi/ms7260/Kconfig b/src/mainboard/msi/ms7260/Kconfig index 0e7e592..e3863a0 100644 --- a/src/mainboard/msi/ms7260/Kconfig +++ b/src/mainboard/msi/ms7260/Kconfig @@ -6,6 +6,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DIMM_DDR2 select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_MCP55 + select HT_CHAIN_DISTRIBUTE select MCP55_USE_NIC select MCP55_USE_AZA select SUPERIO_WINBOND_W83627EHG @@ -39,10 +40,6 @@ config MEM_TRAIN_SEQ int default 2
-config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config MAINBOARD_PART_NUMBER string default "MS-7260" diff --git a/src/mainboard/msi/ms9185/Kconfig b/src/mainboard/msi/ms9185/Kconfig index 0b0ff1c..355fdcf 100644 --- a/src/mainboard/msi/ms9185/Kconfig +++ b/src/mainboard/msi/ms9185/Kconfig @@ -8,6 +8,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_BROADCOM_BCM5780 select SOUTHBRIDGE_BROADCOM_BCM5785 + select HT_CHAIN_DISTRIBUTE select SUPERIO_NSC_PC87417 select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE @@ -34,10 +35,6 @@ config APIC_ID_OFFSET hex default 0x8
-config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config MAINBOARD_PART_NUMBER string default "MS-9185" diff --git a/src/mainboard/msi/ms9282/Kconfig b/src/mainboard/msi/ms9282/Kconfig index f109375..dd96992 100644 --- a/src/mainboard/msi/ms9282/Kconfig +++ b/src/mainboard/msi/ms9282/Kconfig @@ -33,10 +33,6 @@ config APIC_ID_OFFSET hex default 0x10
-config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config MAINBOARD_PART_NUMBER string default "MS-9282" diff --git a/src/mainboard/msi/ms9652_fam10/Kconfig b/src/mainboard/msi/ms9652_fam10/Kconfig index 0b45db3..c64fdda 100644 --- a/src/mainboard/msi/ms9652_fam10/Kconfig +++ b/src/mainboard/msi/ms9652_fam10/Kconfig @@ -16,7 +16,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select BOARD_ROMSIZE_KB_512 select ENABLE_APIC_EXT_ID - select AMDMCT select SB_HT_CHAIN_UNITID_OFFSET_ONLY select QRANK_DIMM_SUPPORT select LIFT_BSP_APIC_ID @@ -77,10 +76,6 @@ config HT_CHAIN_END_UNITID_BASE hex default 0x00
-config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config VAR_MTRR_HOLE bool default n diff --git a/src/mainboard/newisys/khepri/Kconfig b/src/mainboard/newisys/khepri/Kconfig index 7f618af..f1c2687 100644 --- a/src/mainboard/newisys/khepri/Kconfig +++ b/src/mainboard/newisys/khepri/Kconfig @@ -30,10 +30,6 @@ config APIC_ID_OFFSET hex default 0x0
-config SB_HT_CHAIN_ON_BUS0 - int - default 0 - config MAINBOARD_PART_NUMBER string default "Khepri" diff --git a/src/mainboard/nvidia/l1_2pvv/Kconfig b/src/mainboard/nvidia/l1_2pvv/Kconfig index 57911f7..e9664ac 100644 --- a/src/mainboard/nvidia/l1_2pvv/Kconfig +++ b/src/mainboard/nvidia/l1_2pvv/Kconfig @@ -7,6 +7,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DIMM_REGISTERED select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_MCP55 + select HT_CHAIN_DISTRIBUTE select MCP55_USE_NIC select MCP55_USE_AZA select SUPERIO_WINBOND_W83627EHG @@ -43,10 +44,6 @@ config MCP55_NUM int default 2
-config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config MAINBOARD_PART_NUMBER string default "l1_2pvv" diff --git a/src/mainboard/siemens/sitemp_g1p1/Kconfig b/src/mainboard/siemens/sitemp_g1p1/Kconfig index dff329f..d9ad74b 100644 --- a/src/mainboard/siemens/sitemp_g1p1/Kconfig +++ b/src/mainboard/siemens/sitemp_g1p1/Kconfig @@ -43,10 +43,6 @@ config MAX_PHYSICAL_CPUS int default 1
-config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/sunw/ultra40/Kconfig b/src/mainboard/sunw/ultra40/Kconfig index 8f3ff2a..a29cf16 100644 --- a/src/mainboard/sunw/ultra40/Kconfig +++ b/src/mainboard/sunw/ultra40/Kconfig @@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select CPU_AMD_SOCKET_940 select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_CK804 + select HT_CHAIN_DISTRIBUTE select SUPERIO_SMSC_LPC47B397 select SUPERIO_SMSC_LPC47M10X select HAVE_OPTION_TABLE @@ -56,10 +57,6 @@ config HT_CHAIN_UNITID_BASE hex default 0x0
-config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config IRQ_SLOT_COUNT int default 11 diff --git a/src/mainboard/supermicro/h8dme/Kconfig b/src/mainboard/supermicro/h8dme/Kconfig index 52d5581..35f9bf0 100644 --- a/src/mainboard/supermicro/h8dme/Kconfig +++ b/src/mainboard/supermicro/h8dme/Kconfig @@ -7,6 +7,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DIMM_REGISTERED select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_MCP55 + select HT_CHAIN_DISTRIBUTE select MCP55_USE_NIC select MCP55_USE_AZA select SUPERIO_WINBOND_W83627HF @@ -60,10 +61,6 @@ config HT_CHAIN_UNITID_BASE hex default 0x0
-config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config IRQ_SLOT_COUNT int default 11 diff --git a/src/mainboard/supermicro/h8dmr/Kconfig b/src/mainboard/supermicro/h8dmr/Kconfig index f85460b..9efc5d2 100644 --- a/src/mainboard/supermicro/h8dmr/Kconfig +++ b/src/mainboard/supermicro/h8dmr/Kconfig @@ -7,6 +7,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DIMM_REGISTERED select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_MCP55 + select HT_CHAIN_DISTRIBUTE select MCP55_USE_NIC select MCP55_USE_AZA select SUPERIO_WINBOND_W83627HF @@ -59,10 +60,6 @@ config HT_CHAIN_UNITID_BASE hex default 0x0
-config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config IRQ_SLOT_COUNT int default 11 diff --git a/src/mainboard/supermicro/h8dmr_fam10/Kconfig b/src/mainboard/supermicro/h8dmr_fam10/Kconfig index 3a72049..0d20204 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/Kconfig +++ b/src/mainboard/supermicro/h8dmr_fam10/Kconfig @@ -7,6 +7,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DIMM_REGISTERED select NORTHBRIDGE_AMD_AMDFAM10 select SOUTHBRIDGE_NVIDIA_MCP55 + select HT_CHAIN_DISTRIBUTE select MCP55_USE_NIC select MCP55_USE_AZA select SUPERIO_WINBOND_W83627HF @@ -15,7 +16,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select LIFT_BSP_APIC_ID - select AMDMCT select BOARD_ROMSIZE_KB_1024 select ENABLE_APIC_EXT_ID select QRANK_DIMM_SUPPORT @@ -56,10 +56,6 @@ config HT_CHAIN_UNITID_BASE hex default 0x1
-config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config IRQ_SLOT_COUNT int default 11 diff --git a/src/mainboard/supermicro/h8qme_fam10/Kconfig b/src/mainboard/supermicro/h8qme_fam10/Kconfig index b3a1faf..27a74bb 100644 --- a/src/mainboard/supermicro/h8qme_fam10/Kconfig +++ b/src/mainboard/supermicro/h8qme_fam10/Kconfig @@ -8,12 +8,12 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDFAM10 select SOUTHBRIDGE_AMD_AMD8132 select SOUTHBRIDGE_NVIDIA_MCP55 + select HT_CHAIN_DISTRIBUTE select SUPERIO_WINBOND_W83627HF select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select LIFT_BSP_APIC_ID - select AMDMCT select BOARD_ROMSIZE_KB_1024 select ENABLE_APIC_EXT_ID select QRANK_DIMM_SUPPORT @@ -54,10 +54,6 @@ config HT_CHAIN_UNITID_BASE hex default 0x1
-config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config IRQ_SLOT_COUNT int default 11 diff --git a/src/mainboard/supermicro/h8scm_fam10/Kconfig b/src/mainboard/supermicro/h8scm_fam10/Kconfig index 7fbbf66..0673390 100644 --- a/src/mainboard/supermicro/h8scm_fam10/Kconfig +++ b/src/mainboard/supermicro/h8scm_fam10/Kconfig @@ -17,7 +17,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_TABLES select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID - select AMDMCT select BOARD_ROMSIZE_KB_2048 select ENABLE_APIC_EXT_ID
@@ -41,10 +40,6 @@ config MAX_PHYSICAL_CPUS int default 1
-config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/technexion/tim5690/Kconfig b/src/mainboard/technexion/tim5690/Kconfig index 98dce39..0220d77 100644 --- a/src/mainboard/technexion/tim5690/Kconfig +++ b/src/mainboard/technexion/tim5690/Kconfig @@ -37,10 +37,6 @@ config MAX_PHYSICAL_CPUS int default 1
-config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/technexion/tim8690/Kconfig b/src/mainboard/technexion/tim8690/Kconfig index 4e0b25a..ad80e85 100644 --- a/src/mainboard/technexion/tim8690/Kconfig +++ b/src/mainboard/technexion/tim8690/Kconfig @@ -36,10 +36,6 @@ config MAX_PHYSICAL_CPUS int default 1
-config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/tyan/s2850/Kconfig b/src/mainboard/tyan/s2850/Kconfig index e6e3df2..2866b0c 100644 --- a/src/mainboard/tyan/s2850/Kconfig +++ b/src/mainboard/tyan/s2850/Kconfig @@ -40,10 +40,6 @@ config HT_CHAIN_END_UNITID_BASE hex default 0x20
-config SB_HT_CHAIN_ON_BUS0 - int - default 0 - config APIC_ID_OFFSET hex default 0x0 diff --git a/src/mainboard/tyan/s2875/Kconfig b/src/mainboard/tyan/s2875/Kconfig index 30aa01e..85c3ab4 100644 --- a/src/mainboard/tyan/s2875/Kconfig +++ b/src/mainboard/tyan/s2875/Kconfig @@ -42,10 +42,6 @@ config HT_CHAIN_END_UNITID_BASE hex default 0x20
-config SB_HT_CHAIN_ON_BUS0 - int - default 0 - config APIC_ID_OFFSET hex default 0x0 diff --git a/src/mainboard/tyan/s2880/Kconfig b/src/mainboard/tyan/s2880/Kconfig index 5186337..62b4e70 100644 --- a/src/mainboard/tyan/s2880/Kconfig +++ b/src/mainboard/tyan/s2880/Kconfig @@ -22,10 +22,6 @@ config APIC_ID_OFFSET hex default 0x0
-config SB_HT_CHAIN_ON_BUS0 - int - default 0 - config MAINBOARD_PART_NUMBER string default "S2880" diff --git a/src/mainboard/tyan/s2881/Kconfig b/src/mainboard/tyan/s2881/Kconfig index 6c759e1..de641cd 100644 --- a/src/mainboard/tyan/s2881/Kconfig +++ b/src/mainboard/tyan/s2881/Kconfig @@ -6,6 +6,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_AMD_AMD8131 select SOUTHBRIDGE_AMD_AMD8111 + select HT_CHAIN_DISTRIBUTE select SUPERIO_WINBOND_W83627HF select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE @@ -24,10 +25,6 @@ config APIC_ID_OFFSET hex default 0x0
-config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config MAINBOARD_PART_NUMBER string default "S2881" diff --git a/src/mainboard/tyan/s2882/Kconfig b/src/mainboard/tyan/s2882/Kconfig index 646b5a8..bf980d7 100644 --- a/src/mainboard/tyan/s2882/Kconfig +++ b/src/mainboard/tyan/s2882/Kconfig @@ -23,10 +23,6 @@ config APIC_ID_OFFSET hex default 0x0
-config SB_HT_CHAIN_ON_BUS0 - int - default 0 - config MAINBOARD_PART_NUMBER string default "S2882" diff --git a/src/mainboard/tyan/s2885/Kconfig b/src/mainboard/tyan/s2885/Kconfig index 86e43f8..b218ab7 100644 --- a/src/mainboard/tyan/s2885/Kconfig +++ b/src/mainboard/tyan/s2885/Kconfig @@ -7,6 +7,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_AMD_AMD8111 select SOUTHBRIDGE_AMD_AMD8131 select SOUTHBRIDGE_AMD_AMD8151 + select HT_CHAIN_DISTRIBUTE select SUPERIO_WINBOND_W83627HF select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE @@ -23,10 +24,6 @@ config APIC_ID_OFFSET hex default 0x10
-config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config MAINBOARD_PART_NUMBER string default "S2885" diff --git a/src/mainboard/tyan/s2891/Kconfig b/src/mainboard/tyan/s2891/Kconfig index 3d1c1fb..238f5bc 100644 --- a/src/mainboard/tyan/s2891/Kconfig +++ b/src/mainboard/tyan/s2891/Kconfig @@ -6,6 +6,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_CK804 select SOUTHBRIDGE_AMD_AMD8131 + select HT_CHAIN_DISTRIBUTE select SUPERIO_WINBOND_W83627HF select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE @@ -23,10 +24,6 @@ config APIC_ID_OFFSET hex default 0x10
-config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config MAINBOARD_PART_NUMBER string default "S2891" diff --git a/src/mainboard/tyan/s2892/Kconfig b/src/mainboard/tyan/s2892/Kconfig index b9c4105..cbe076c 100644 --- a/src/mainboard/tyan/s2892/Kconfig +++ b/src/mainboard/tyan/s2892/Kconfig @@ -6,6 +6,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_CK804 select SOUTHBRIDGE_AMD_AMD8131 + select HT_CHAIN_DISTRIBUTE select SUPERIO_WINBOND_W83627HF select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE @@ -43,10 +44,6 @@ config HT_CHAIN_END_UNITID_BASE hex default 0x20
-config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config IRQ_SLOT_COUNT int default 11 diff --git a/src/mainboard/tyan/s2895/Kconfig b/src/mainboard/tyan/s2895/Kconfig index 544b0c5..21db63c 100644 --- a/src/mainboard/tyan/s2895/Kconfig +++ b/src/mainboard/tyan/s2895/Kconfig @@ -6,6 +6,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_CK804 select SOUTHBRIDGE_AMD_AMD8131 + select HT_CHAIN_DISTRIBUTE select SUPERIO_SMSC_LPC47B397 select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE @@ -47,10 +48,6 @@ config HT_CHAIN_END_UNITID_BASE hex default 0x20
-config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config IRQ_SLOT_COUNT int default 11 diff --git a/src/mainboard/tyan/s2912/Kconfig b/src/mainboard/tyan/s2912/Kconfig index 26d9a53..7ad1a1c 100644 --- a/src/mainboard/tyan/s2912/Kconfig +++ b/src/mainboard/tyan/s2912/Kconfig @@ -7,6 +7,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DIMM_REGISTERED select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_MCP55 + select HT_CHAIN_DISTRIBUTE select MCP55_USE_NIC select SUPERIO_WINBOND_W83627HF select PARALLEL_CPU_INIT @@ -38,10 +39,6 @@ config MEM_TRAIN_SEQ int default 1
-config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config MAINBOARD_PART_NUMBER string default "S2912" diff --git a/src/mainboard/tyan/s2912_fam10/Kconfig b/src/mainboard/tyan/s2912_fam10/Kconfig index 91a6e0d..b5e31fa 100644 --- a/src/mainboard/tyan/s2912_fam10/Kconfig +++ b/src/mainboard/tyan/s2912_fam10/Kconfig @@ -7,6 +7,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DIMM_REGISTERED select NORTHBRIDGE_AMD_AMDFAM10 select SOUTHBRIDGE_NVIDIA_MCP55 + select HT_CHAIN_DISTRIBUTE select MCP55_USE_NIC select SUPERIO_WINBOND_W83627HF select PARALLEL_CPU_INIT @@ -16,7 +17,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select LIFT_BSP_APIC_ID select BOARD_ROMSIZE_KB_1024 select ENABLE_APIC_EXT_ID - select AMDMCT select MMCONF_SUPPORT_DEFAULT select QRANK_DIMM_SUPPORT
@@ -36,10 +36,6 @@ config APIC_ID_OFFSET hex default 0
-config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config MAINBOARD_PART_NUMBER string default "S2912 (Fam10)" diff --git a/src/mainboard/tyan/s4880/Kconfig b/src/mainboard/tyan/s4880/Kconfig index d4feacb..6c85c6c 100644 --- a/src/mainboard/tyan/s4880/Kconfig +++ b/src/mainboard/tyan/s4880/Kconfig @@ -30,10 +30,6 @@ config APIC_ID_OFFSET hex default 0x10
-config SB_HT_CHAIN_ON_BUS0 - int - default 0 - config MAINBOARD_PART_NUMBER string default "S4880" diff --git a/src/mainboard/tyan/s4882/Kconfig b/src/mainboard/tyan/s4882/Kconfig index 2bd3854..7723acf 100644 --- a/src/mainboard/tyan/s4882/Kconfig +++ b/src/mainboard/tyan/s4882/Kconfig @@ -30,10 +30,6 @@ config APIC_ID_OFFSET hex default 0x10
-config SB_HT_CHAIN_ON_BUS0 - int - default 0 - config MAINBOARD_PART_NUMBER string default "S4882" diff --git a/src/mainboard/winent/mb6047/Kconfig b/src/mainboard/winent/mb6047/Kconfig index 86b0ae0..622441e 100644 --- a/src/mainboard/winent/mb6047/Kconfig +++ b/src/mainboard/winent/mb6047/Kconfig @@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select CPU_AMD_SOCKET_940 select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_CK804 + select HT_CHAIN_DISTRIBUTE select SUPERIO_WINBOND_W83627THG select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE @@ -25,10 +26,6 @@ config APIC_ID_OFFSET hex default 0x10
-config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config MAINBOARD_PART_NUMBER string default "MB6047" diff --git a/src/northbridge/amd/amdfam10/Kconfig b/src/northbridge/amd/amdfam10/Kconfig index 8e1c4f8..1281f43 100644 --- a/src/northbridge/amd/amdfam10/Kconfig +++ b/src/northbridge/amd/amdfam10/Kconfig @@ -33,10 +33,6 @@ config AGP_APERTURE_SIZE hex default 0x4000000
-config AMDMCT - bool - default y - config HW_MEM_HOLE_SIZEK hex default 0x100000 @@ -70,6 +66,9 @@ config SB_HT_CHAIN_UNITID_OFFSET_ONLY bool default n
+config HT_CHAIN_DISTRIBUTE + def_bool n + config DIMM_FBDIMM bool default n diff --git a/src/northbridge/amd/amdfam10/Makefile.inc b/src/northbridge/amd/amdfam10/Makefile.inc index ef4bef4..4c9d3f0 100644 --- a/src/northbridge/amd/amdfam10/Makefile.inc +++ b/src/northbridge/amd/amdfam10/Makefile.inc @@ -1,5 +1,6 @@ ramstage-y += northbridge.c ramstage-y += misc_control.c +ramstage-y += ht_config.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h index ab4b42e..96f182d 100644 --- a/src/northbridge/amd/amdfam10/amdfam10.h +++ b/src/northbridge/amd/amdfam10/amdfam10.h @@ -976,41 +976,10 @@ that are corresponding to 0x01, 0x02, 0x03, 0x05, 0x06, 0x07
#include "raminit.h"
-#if !CONFIG_AMDMCT - -//struct definitions - -struct dimm_size { - u8 per_rank; // it is rows + col + bank_lines + data lines */ - u8 rows; - u8 col; - u8 bank; //1, 2, 3 mean 2, 4, 8 - u8 rank; -} __attribute__((packed)); - -struct mem_info { // pernode - u32 dimm_mask; - struct dimm_size sz[DIMM_SOCKETS*2]; // for ungang support - u32 x4_mask; - u32 x16_mask; - u32 single_rank_mask; - u32 page_1k_mask; -// u32 ecc_mask; -// u32 registered_mask; - u8 is_opteron; - u8 is_registered; //don't support mixing on the same channel or between channel - u8 is_ecc; //don't support mixing on the same channel or between channel - u8 is_Width128; - u8 memclk_set; // we need to use this to retrieve the mem param, all dimms need to work at same freq for one node - u8 is_cs_interleaved[2]; //cs - u8 rsv[1]; -} __attribute__((packed)); -#else - #if (CONFIG_DIMM_SUPPORT & 0x000F)==0x0005 /* AMD_FAM10_DDR3 */ +#if (CONFIG_DIMM_SUPPORT & 0x000F)==0x0005 /* AMD_FAM10_DDR3 */ #include "../amdmct/mct_ddr3/mct_d.h" - #else +#else #include "../amdmct/mct/mct_d.h" - #endif #endif
struct link_pair_t { @@ -1034,13 +1003,6 @@ struct nodes_info_t { } __attribute__((packed));
/* be careful with the alignment of sysinfo, bacause sysinfo may be shared by coreboot_car and ramstage stage. and ramstage may be running at 64bit later.*/ -#if !CONFIG_AMDMCT - -//#define MEM_CS_COPY 1 -#define MEM_CS_COPY NODE_NUMS -#define DQS_DELAY_COPY NODE_NUMS -#endif -
struct sys_info { int32_t needs_reset; @@ -1066,29 +1028,8 @@ struct sys_info {
struct mem_controller ctrl[NODE_NUMS];
-#if CONFIG_AMDMCT -// sMCTStruct MCTData; -// sDCTStruct *DCTNodeData[NODE_NUMS]; -// sDCTStruct DCTNodeData_a[NODE_NUMS]; struct MCTStatStruc MCTstat; struct DCTStatStruc DCTstatA[NODE_NUMS]; -#else - - u8 ctrl_present[NODE_NUMS]; - struct mem_info meminfo[NODE_NUMS]; - u8 mem_trained[NODE_NUMS]; //0: no dimm, 1: trained, 0x80: not started, 0x81: recv1 fail, 0x82: Pos Fail, 0x83:recv2 fail - u32 tom_m; - u32 tom2_m; - - //if we are getting tight of global space, may need to squesh following to one copy - u32 mem_base[MEM_CS_COPY][2]; // two dct - u32 cs_base[MEM_CS_COPY][2][8]; //8 cs_idx - u32 hole_startk; // 0 mean hole - - u8 dqs_delay_a[DQS_DELAY_COPY*2*4*2*9]; //8 node, channel 2, dimm 4, direction 2 , bytelane *9 - u8 dqs_rcvr_dly_a[DQS_DELAY_COPY*2*4*9]; //8 node, channel 2, dimm 4, bytelane *9 - u8 dqs_rcvr_dly_a_1[9]; //8 node, channel 2, dimm 4, bytelane *9 -#endif
} __attribute__((packed));
@@ -1100,78 +1041,6 @@ extern struct sys_info sysinfo_car; device_t get_node_pci(u32 nodeid, u32 fn); #endif
-#if !CONFIG_AMDMCT - -#ifdef __PRE_RAM__ -static void soft_reset(void); -#endif -static void wait_all_core0_mem_trained(struct sys_info *sysinfo) -{ - int i; - u32 mask_lo = 0; - u32 mask_hi = 0; - unsigned needs_reset = 0; - - if(sysinfo->nodes == 1) return; // in case only one cpu installed - for(i=1; i<sysinfo->nodes; i++) { - /* Skip everything if I don't have any memory on this controller */ - if(sysinfo->mem_trained[i]==0x00) continue; - - if(i<32) { - mask_lo |= (1<<i); - } else { - mask_hi |= (1<<(i-32)); - } - } - - i = 1; - while(1) { - if(i<32) { - if(mask_lo & (1<<i)) { - if(sysinfo->mem_trained[i] != 0x80) { - mask_lo &= ~(1<<i); - } - } - } else { - if(mask_hi & (1<<(i-32))) { - if(sysinfo->mem_trained[i] != 0x80) { - mask_hi &= ~(1<<(i-32)); - } - } - } - - if((!mask_lo) && (!mask_hi)) break; - - i++; - i%=sysinfo->nodes; - } - - for(i=0; i<sysinfo->nodes; i++) { - printk(BIOS_DEBUG, "mem_trained[%02x]=%02x\n", i, sysinfo->mem_trained[i]); - switch(sysinfo->mem_trained[i]) { - case 0: //don't need train - case 1: //trained - break; - case 0x81: //recv1: fail - case 0x82: //Pos :fail - case 0x83: //recv2: fail - needs_reset = 1; - break; - } - } - if(needs_reset) { - printk(BIOS_DEBUG, "mem trained failed\n"); -#ifdef __PRE_RAM__ - soft_reset(); -#else - hard_reset(); -#endif - } - -} - -#endif - #ifdef __PRE_RAM__ void showallroutes(int level, device_t dev);
diff --git a/src/northbridge/amd/amdfam10/conf.c b/src/northbridge/amd/amdfam10/conf.c deleted file mode 100644 index 6688e0a..0000000 --- a/src/northbridge/amd/amdfam10/conf.c +++ /dev/null @@ -1,612 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#if defined(__PRE_RAM__) -typedef struct sys_info sys_info_conf_t; -#else -typedef struct amdfam10_sysconf_t sys_info_conf_t; -#endif - -struct dram_base_mask_t { - u32 base; //[47:27] at [28:8] - u32 mask; //[47:27] at [28:8] and enable at bit 0 -}; - -static struct dram_base_mask_t get_dram_base_mask(u32 nodeid) -{ - device_t dev; - struct dram_base_mask_t d; -#if defined(__PRE_RAM__) - dev = PCI_DEV(CONFIG_CBB, CONFIG_CDB, 1); -#else - dev = __f1_dev[0]; -#endif - - u32 temp; - temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16] - d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too - temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] - d.mask |= temp<<21; - - temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16] - d.mask |= (temp & 1); // enable bit - - d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too - temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] - d.base |= temp<<21; - return d; -} - -#if !CONFIG_AMDMCT -static void set_dram_base_mask(u32 nodeid, struct dram_base_mask_t d, u32 nodes) -{ - u32 i; - device_t dev; - u32 d_base_lo, d_base_hi, d_mask_lo, d_mask_hi; - u32 d_base_lo_reg, d_base_hi_reg, d_mask_lo_reg, d_mask_hi_reg; - d_mask_lo = (((d.mask<<(8+3))|(0x07<<16)) & 0xffff0000)|nodeid; // need to fill DramMask[26:24] with ones - d_mask_hi = (d.mask>>21) & 0xff; - d_base_lo = ((d.base<<(8+3)) & 0xffff0000); - if (d.mask & 1) d_base_lo |= 3; - d_base_hi = (d.base>>21) & 0xff; - d_mask_lo_reg = 0x44+(nodeid<<3); - d_mask_hi_reg = 0x144+(nodeid<<3); - d_base_lo_reg = 0x40+(nodeid<<3); - d_base_hi_reg = 0x140+(nodeid<<3); - - for (i=0;i<nodes;i++) { -#if defined(__PRE_RAM__) - dev = NODE_PCI(i, 1); -#else - dev = __f1_dev[i]; -#endif - pci_write_config32(dev, d_mask_lo_reg, d_mask_lo); // need to fill DramMask[26:24] with ones - pci_write_config32(dev, d_mask_hi_reg, d_mask_hi); - pci_write_config32(dev, d_base_lo_reg, d_base_lo); - pci_write_config32(dev, d_base_hi_reg, d_base_hi); - } - -#if defined(__PRE_RAM__) - dev = NODE_PCI(nodeid, 1); -#else - dev = __f1_dev[nodeid]; -#endif - pci_write_config32(dev, 0x120, d.base>>8); - pci_write_config32(dev, 0x124, d.mask>>8); - -} -#endif - -#if !CONFIG_AMDMCT -static void set_DctSelBaseAddr(u32 i, u32 sel_m) -{ - device_t dev; -#if defined(__PRE_RAM__) - dev = NODE_PCI(i, 2); -#else - dev = __f2_dev[i]; -#endif - u32 dcs_lo; - dcs_lo = pci_read_config32(dev, DRAM_CTRL_SEL_LOW); - dcs_lo &= ~(DCSL_DctSelBaseAddr_47_27_MASK<<DCSL_DctSelBaseAddr_47_27_SHIFT); - dcs_lo |= (sel_m<<(20+DCSL_DctSelBaseAddr_47_27_SHIFT-27)); - pci_write_config32(dev, DRAM_CTRL_SEL_LOW, dcs_lo); - -} - - -static u32 get_DctSelBaseAddr(u32 i) -{ - device_t dev; -#if defined(__PRE_RAM__) - dev = NODE_PCI(i, 2); -#else - dev = __f2_dev[i]; -#endif - u32 sel_m; - u32 dcs_lo; - dcs_lo = pci_read_config32(dev, DRAM_CTRL_SEL_LOW); - dcs_lo &= DCSL_DctSelBaseAddr_47_27_MASK<<DCSL_DctSelBaseAddr_47_27_SHIFT; - sel_m = dcs_lo>>(20+DCSL_DctSelBaseAddr_47_27_SHIFT-27); - return sel_m; -} - -#ifdef UNUSED_CODE -static void set_DctSelHiEn(u32 i, u32 val) -{ - device_t dev; -#if defined(__PRE_RAM__) - dev = NODE_PCI(i, 2); -#else - dev = __f2_dev[i]; -#endif - u32 dcs_lo; - dcs_lo = pci_read_config32(dev, DRAM_CTRL_SEL_LOW); - dcs_lo &= ~(7); - dcs_lo |= (val & 7); - pci_write_config32(dev, DRAM_CTRL_SEL_LOW, dcs_lo); - -} -#endif - -static u32 get_DctSelHiEn(u32 i) -{ - device_t dev; -#if defined(__PRE_RAM__) - dev = NODE_PCI(i, 2); -#else - dev = __f2_dev[i]; -#endif - u32 dcs_lo; - dcs_lo = pci_read_config32(dev, DRAM_CTRL_SEL_LOW); - dcs_lo &= 7; - return dcs_lo; - -} - -static void set_DctSelBaseOffset(u32 i, u32 sel_off_m) -{ - device_t dev; -#if defined(__PRE_RAM__) - dev = NODE_PCI(i, 2); -#else - dev = __f2_dev[i]; -#endif - u32 dcs_hi; - dcs_hi = pci_read_config32(dev, DRAM_CTRL_SEL_HIGH); - dcs_hi &= ~(DCSH_DctSelBaseOffset_47_26_MASK<<DCSH_DctSelBaseOffset_47_26_SHIFT); - dcs_hi |= sel_off_m<<(20+DCSH_DctSelBaseOffset_47_26_SHIFT-26); - pci_write_config32(dev, DRAM_CTRL_SEL_HIGH, dcs_hi); - -} - -#ifdef UNUSED_CODE -static u32 get_DctSelBaseOffset(u32 i) -{ - device_t dev; -#if defined(__PRE_RAM__) - dev = NODE_PCI(i, 2); -#else - dev = __f2_dev[i]; -#endif - u32 sel_off_m; - u32 dcs_hi; - dcs_hi = pci_read_config32(dev, DRAM_CTRL_SEL_HIGH); - dcs_hi &= DCSH_DctSelBaseOffset_47_26_MASK<<DCSH_DctSelBaseOffset_47_26_SHIFT; - sel_off_m = dcs_hi>>(20+DCSH_DctSelBaseOffset_47_26_SHIFT-26); - return sel_off_m; -} -#endif - -static u32 get_one_DCT(struct mem_info *meminfo) -{ - u32 one_DCT = 1; - if (meminfo->is_Width128) { - one_DCT = 1; - } else { - u32 dimm_mask = meminfo->dimm_mask; - if ((dimm_mask >> DIMM_SOCKETS) && (dimm_mask & ((1<<DIMM_SOCKETS)-1))) { - one_DCT = 0; - } - } - - return one_DCT; -} - -#if CONFIG_HW_MEM_HOLE_SIZEK != 0 -// See that other copy in northbridge.c -static u32 hoist_memory(u32 hole_startk, u32 i, u32 one_DCT, u32 nodes) -{ - u32 ii; - u32 carry_over; - device_t dev; - struct dram_base_mask_t d; - u32 sel_m; - u32 sel_hi_en; - u32 hoist; - - - carry_over = (4*1024*1024) - hole_startk; - - for (ii=nodes - 1;ii>i;ii--) { - d = get_dram_base_mask(ii); - if (!(d.mask & 1)) continue; - d.base += (carry_over>>9); - d.mask += (carry_over>>9); - set_dram_base_mask(ii, d, nodes); - - if (get_DctSelHiEn(ii) & 1) { - sel_m = get_DctSelBaseAddr(ii); - sel_m += carry_over>>10; - set_DctSelBaseAddr(ii, sel_m); - } - - } - d = get_dram_base_mask(i); - d.mask += (carry_over>>9); - set_dram_base_mask(i,d, nodes); -#if defined(__PRE_RAM__) - dev = NODE_PCI(i, 1); -#else - dev = __f1_dev[i]; -#endif - sel_hi_en = get_DctSelHiEn(i); - if (sel_hi_en & 1) { - sel_m = get_DctSelBaseAddr(i); - } - if (d.base == (hole_startk>>9)) { - //don't need set memhole here, because hole off set will be 0, overflow - //so need to change base reg instead, new basek will be 4*1024*1024 - d.base = (4*1024*1024)>>9; - set_dram_base_mask(i, d, nodes); - - if (sel_hi_en & 1) { - sel_m += carry_over>>10; - set_DctSelBaseAddr(i, sel_m); - } - } else { - hoist = /* hole start address */ - ((hole_startk << 10) & 0xff000000) + - /* enable */ - 1; - if (one_DCT||(sel_m>=(hole_startk>>10))) { //one DCT or hole in DCT0 - hoist += - /* hole address to memory controller address */ - ((((d.base<<9) + carry_over) >> 6) & 0x0000ff00) ; - - if (sel_hi_en & 1) { - sel_m += (carry_over>>10); - set_DctSelBaseAddr(i, sel_m); - set_DctSelBaseOffset(i, sel_m); - } - } else { // hole in DCT1 range - hoist += - /* hole address to memory controller address */ - ((((sel_m<<10) + carry_over) >> 6) & 0x0000ff00) ; - // don't need to update DctSelBaseAddr - if (sel_hi_en & 1) { - set_DctSelBaseOffset(i, sel_m); - } - } - pci_write_config32(dev, 0xf0, hoist); - - } - - return carry_over; -} -#endif -#endif // CONFIG_AMDMCT - - -static void set_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index, - u32 busn_min, u32 busn_max, u32 segbit, - u32 nodes) -{ - u32 tempreg; - u32 i; - device_t dev; - - busn_min>>=segbit; - busn_max>>=segbit; - - tempreg = 3 | ((nodeid&0xf)<<4) | ((nodeid & 0x30)<<(12-4))|(linkn<<8)|((busn_min & 0xff)<<16)|((busn_max&0xff)<<24); - for (i=0; i<nodes; i++) { - #if defined(__PRE_RAM__) - dev = NODE_PCI(i, 1); - #else - dev = __f1_dev[i]; - #endif - pci_write_config32(dev, 0xe0 + ht_c_index * 4, tempreg); - } -} - -static void clear_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index, - u32 busn_min, u32 busn_max, u32 nodes) -{ - u32 i; - device_t dev; - - for (i=0; i<nodes; i++) { - #if defined(__PRE_RAM__) - dev = NODE_PCI(i, 1); - #else - dev = __f1_dev[i]; - #endif - pci_write_config32(dev, 0xe0 + ht_c_index * 4, 0); - } -} - -#if CONFIG_PCI_BUS_SEGN_BITS -static u32 check_segn(device_t dev, u32 segbusn, u32 nodes, - sys_info_conf_t *sysinfo) -{ - //check segbusn here, We need every node have the same segn - if ((segbusn & 0xff)>(0xe0-1)) {// use next segn - u32 segn = (segbusn >> 8) & 0x0f; - segn++; - segbusn = segn<<8; - } - if (segbusn>>8) { - u32 val; - val = pci_read_config32(dev, 0x160); - val &= ~(0xf<<25); - val |= (segbusn & 0xf00)<<(25-8); - pci_write_config32(dev, 0x160, val); - } - - return segbusn; -} -#endif - -#if defined(__PRE_RAM__) -static void set_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index, - u32 io_min, u32 io_max, u32 nodes) -{ - u32 i; - u32 tempreg; - device_t dev; - - /* io range allocation */ - tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit - for (i=0; i<nodes; i++) { - #if defined(__PRE_RAM__) - dev = NODE_PCI(i, 1); - #else - dev = __f1_dev[i]; - #endif - pci_write_config32(dev, 0xC4 + ht_c_index * 8, tempreg); - } - tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? - for (i=0; i<nodes; i++) { - #if defined(__PRE_RAM__) - dev = NODE_PCI(i, 1); - #else - dev = __f1_dev[i]; - #endif - pci_write_config32(dev, 0xC0 + ht_c_index * 8, tempreg); - } -} - - -static void clear_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index, - u32 io_min, u32 io_max, u32 nodes) -{ - u32 i; - device_t dev; - /* io range allocation */ - for (i=0; i<nodes; i++) { - #if defined(__PRE_RAM__) - dev = NODE_PCI(i, 1); - #else - dev = __f1_dev[i]; - #endif - pci_write_config32(dev, 0xC4 + ht_c_index * 8, 0); - pci_write_config32(dev, 0xC0 + ht_c_index * 8, 0); - } -} -#endif - -#ifdef UNUSED_CODE -static void re_set_all_config_map_reg(u32 nodes, u32 segbit, - sys_info_conf_t *sysinfo) -{ - u32 ht_c_index; - device_t dev; - - set_config_map_reg(0, sysinfo->sblk, 0, 0, sysinfo->ht_c_conf_bus[0]>>20, segbit, nodes); - - /* clean others */ - for (ht_c_index=1;ht_c_index<4; ht_c_index++) { - u32 i; - for (i=0; i<nodes; i++) { - #if defined(__PRE_RAM__) - dev = NODE_PCI(i, 1); - #else - dev = __f1_dev[i]; - #endif - pci_write_config32(dev, 0xe0 + ht_c_index * 4, 0); - } - } - - for (ht_c_index = 1; ht_c_index<sysinfo->ht_c_num; ht_c_index++) { - u32 nodeid, linkn; - u32 busn_max; - u32 busn_min; - nodeid = (sysinfo->ht_c_conf_bus[ht_c_index] >> 2) & 0x3f; - linkn = (sysinfo->ht_c_conf_bus[ht_c_index]>>8) & 0x7; - busn_max = sysinfo->ht_c_conf_bus[ht_c_index]>>20; - busn_min = (sysinfo->ht_c_conf_bus[ht_c_index]>>12) & 0xff; - busn_min |= busn_max & 0xf00; - set_config_map_reg(nodeid, linkn, ht_c_index, busn_min, busn_max, segbit, nodes); - } - -} -#endif - -static u32 get_ht_c_index(u32 nodeid, u32 linkn, sys_info_conf_t *sysinfo) -{ - u32 tempreg; - u32 ht_c_index = 0; - -#if 0 - tempreg = 3 | ((nodeid & 0xf) <<4) | ((nodeid & 0x30)<<(12-4)) | (linkn<<8); - - for (ht_c_index=0;ht_c_index<4; ht_c_index++) { - reg = pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 1), 0xe0 + ht_c_index * 4); - if (((reg & 0xffff) == 0x0000)) { /*found free*/ - break; - } - } -#endif - tempreg = 3 | ((nodeid & 0x3f)<<2) | (linkn<<8); - for (ht_c_index=0; ht_c_index<32; ht_c_index++) { - if ((sysinfo->ht_c_conf_bus[ht_c_index] & 0xfff) == tempreg) { - return ht_c_index; - } - } - - for (ht_c_index=0; ht_c_index<32; ht_c_index++) { - if (sysinfo->ht_c_conf_bus[ht_c_index] == 0) { - return ht_c_index; - } - } - - return -1; -} - -static void store_ht_c_conf_bus(u32 nodeid, u32 linkn, u32 ht_c_index, - u32 busn_min, u32 busn_max, - sys_info_conf_t *sysinfo) -{ - u32 val; - val = 3 | ((nodeid & 0x3f)<<2) | (linkn<<8); - sysinfo->ht_c_conf_bus[ht_c_index] = val | ((busn_min & 0xff) <<12) | (busn_max<<20); // same node need segn are same - -} - -#ifdef UNUSED_CODE -static void set_BusSegmentEn(u32 node, u32 segbit) -{ -#if CONFIG_PCI_BUS_SEGN_BITS - u32 dword; - device_t dev; - -#if defined(__PRE_RAM__) - dev = NODE_PCI(node, 0); -#else - dev = __f0_dev[node]; -#endif - - dword = pci_read_config32(dev, 0x68); - dword &= ~(7<<28); - dword |= (segbit<<28); /* bus segment enable */ - pci_write_config32(dev, 0x68, dword); -#endif -} -#endif - -#if !defined(__PRE_RAM__) -static u32 get_io_addr_index(u32 nodeid, u32 linkn) -{ - u32 index; - - for (index=0; index<256; index++) { - if (sysconf.conf_io_addrx[index+4] == 0) { - sysconf.conf_io_addr[index+4] = (nodeid & 0x3f) ; - sysconf.conf_io_addrx[index+4] = 1 | ((linkn & 0x7)<<4); - return index; - } - } - - return 0; -} - -static u32 get_mmio_addr_index(u32 nodeid, u32 linkn) -{ - u32 index; - - for (index=0; index<64; index++) { - if (sysconf.conf_mmio_addrx[index+8] == 0) { - sysconf.conf_mmio_addr[index+8] = (nodeid & 0x3f) ; - sysconf.conf_mmio_addrx[index+8] = 1 | ((linkn & 0x7)<<4); - return index; - } - } - - return 0; -} - -static void store_conf_io_addr(u32 nodeid, u32 linkn, u32 reg, u32 index, - u32 io_min, u32 io_max) -{ - u32 val; - - /* io range allocation */ - index = (reg-0xc0)>>3; - - val = (nodeid & 0x3f); // 6 bits used - sysconf.conf_io_addr[index] = val | ((io_max<<8) & 0xfffff000); //limit : with nodeid - val = 3 | ((linkn & 0x7)<<4) ; // 8 bits used - sysconf.conf_io_addrx[index] = val | ((io_min<<8) & 0xfffff000); // base : with enable bit - - if (sysconf.io_addr_num < (index+1)) - sysconf.io_addr_num = index+1; -} - - -static void store_conf_mmio_addr(u32 nodeid, u32 linkn, u32 reg, u32 index, - u32 mmio_min, u32 mmio_max) -{ - u32 val; - - /* io range allocation */ - index = (reg-0x80)>>3; - - val = (nodeid & 0x3f) ; // 6 bits used - sysconf.conf_mmio_addr[index] = val | (mmio_max & 0xffffff00); //limit : with nodeid and linkn - val = 3 | ((linkn & 0x7)<<4) ; // 8 bits used - sysconf.conf_mmio_addrx[index] = val | (mmio_min & 0xffffff00); // base : with enable bit - - if ( sysconf.mmio_addr_num<(index+1)) - sysconf.mmio_addr_num = index+1; -} - - -static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, - u32 io_min, u32 io_max) -{ - u32 i; - u32 tempreg; - - /* io range allocation */ - tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit - for (i=0; i<sysconf.nodes; i++) - pci_write_config32(__f1_dev[i], reg+4, tempreg); - - tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? -#if 0 - // FIXME: can we use VGA reg instead? - if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { - printk(BIOS_SPEW, "%s, enabling legacy VGA IO forwarding for %s link %s\n", - __func__, dev_path(dev), link); - tempreg |= PCI_IO_BASE_VGA_EN; - } - if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_NO_ISA) { - tempreg |= PCI_IO_BASE_NO_ISA; - } -#endif - for (i=0; i<sysconf.nodes; i++) - pci_write_config32(__f1_dev[i], reg, tempreg); -} - -static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmio_min, u32 mmio_max, u32 nodes) -{ - u32 i; - u32 tempreg; - - /* io range allocation */ - tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit - for (i=0; i<nodes; i++) - pci_write_config32(__f1_dev[i], reg+4, tempreg); - tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); - for (i=0; i<sysconf.nodes; i++) - pci_write_config32(__f1_dev[i], reg, tempreg); -} - -#endif diff --git a/src/northbridge/amd/amdfam10/debug.c b/src/northbridge/amd/amdfam10/debug.c index d1fdaf8..6aed390 100644 --- a/src/northbridge/amd/amdfam10/debug.c +++ b/src/northbridge/amd/amdfam10/debug.c @@ -33,11 +33,7 @@ static inline void print_debug_addr(const char *str, void *val)
static void print_debug_pci_dev(u32 dev) { -#if !CONFIG_PCI_BUS_SEGN_BITS printk(BIOS_DEBUG, "PCI: %02x:%02x.%02x", (dev>>20) & 0xff, (dev>>15) & 0x1f, (dev>>12) & 0x7); -#else - printk(BIOS_DEBUG, "PCI: %04x:%02x:%02x.%02x", (dev>>28) & 0x0f, (dev>>20) & 0xff, (dev>>15) & 0x1f, (dev>>12) & 0x7); -#endif }
static inline void print_pci_devices(void) diff --git a/src/northbridge/amd/amdfam10/ht_config.c b/src/northbridge/amd/amdfam10/ht_config.c new file mode 100644 index 0000000..57b2d0a --- /dev/null +++ b/src/northbridge/amd/amdfam10/ht_config.c @@ -0,0 +1,236 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <stdint.h> +#include <device/device.h> +#include <device/pci_ops.h> + +#include <cpu/amd/amdfam10_sysconf.h> +#include "northbridge.h" +#include "amdfam10.h" +#include "ht_config.h" + +struct dram_base_mask_t get_dram_base_mask(u32 nodeid) +{ + struct dram_base_mask_t d; + device_t dev = __f1_dev[0]; + + u32 temp; + temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16] + d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too + temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] + d.mask |= temp<<21; + + temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16] + d.mask |= (temp & 1); // enable bit + + d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too + temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] + d.base |= temp<<21; + return d; +} + +void set_config_map_reg(struct bus *link) +{ + u32 tempreg; + u32 i; + u32 ht_c_index = get_ht_c_index(link); + u32 linkn = link->link_num & 0x0f; + u32 busn_min = (link->secondary >> sysconf.segbit) & 0xff; + u32 busn_max = (link->subordinate >> sysconf.segbit) & 0xff; + u32 nodeid = amdfam10_nodeid(link->dev); + + tempreg = ((nodeid & 0x30) << (12-4)) | ((nodeid & 0xf) << 4) | 3; + tempreg |= (busn_max << 24)|(busn_min << 16)|(linkn << 8); + + for (i=0; i < sysconf.nodes; i++) { + device_t dev = __f1_dev[i]; + pci_write_config32(dev, 0xe0 + ht_c_index * 4, tempreg); + } +} + +void clear_config_map_reg(struct bus *link) +{ + u32 i; + u32 ht_c_index = get_ht_c_index(link); + + for (i=0; i < sysconf.nodes; i++) { + device_t dev = __f1_dev[i]; + pci_write_config32(dev, 0xe0 + ht_c_index * 4, 0); + } +} + + +static u32 ht_c_key(struct bus *link) +{ + u32 nodeid = amdfam10_nodeid(link->dev); + u32 linkn = link->link_num & 0x0f; + u32 val = (linkn << 8) | ((nodeid & 0x3f) << 2) | 3; + return val; +} + +static u32 get_ht_c_index_by_key(u32 key, sys_info_conf_t *sysinfo) +{ + u32 ht_c_index = 0; + + for (ht_c_index=0; ht_c_index<32; ht_c_index++) { + if ((sysinfo->ht_c_conf_bus[ht_c_index] & 0xfff) == key) { + return ht_c_index; + } + } + + for (ht_c_index=0; ht_c_index<32; ht_c_index++) { + if (sysinfo->ht_c_conf_bus[ht_c_index] == 0) { + return ht_c_index; + } + } + + return -1; +} + +u32 get_ht_c_index(struct bus *link) +{ + u32 val = ht_c_key(link); + return get_ht_c_index_by_key(val, &sysconf); +} + +void store_ht_c_conf_bus(struct bus *link) +{ + u32 val = ht_c_key(link); + u32 ht_c_index = get_ht_c_index_by_key(val, &sysconf); + + u32 segn = (link->subordinate >> 8) & 0x0f; + u32 busn_min = link->secondary & 0xff; + u32 busn_max = link->subordinate & 0xff; + + val |= (segn << 28) | (busn_max << 20) | (busn_min << 12); + + sysconf.ht_c_conf_bus[ht_c_index] = val; + sysconf.hcdn_reg[ht_c_index] = link->hcdn_reg; + sysconf.ht_c_num++; +} + +u32 get_io_addr_index(u32 nodeid, u32 linkn) +{ + u32 index; + + for (index=0; index<256; index++) { + if (sysconf.conf_io_addrx[index+4] == 0) { + sysconf.conf_io_addr[index+4] = (nodeid & 0x3f) ; + sysconf.conf_io_addrx[index+4] = 1 | ((linkn & 0x7)<<4); + return index; + } + } + + return 0; +} + +u32 get_mmio_addr_index(u32 nodeid, u32 linkn) +{ + u32 index; + + for (index=0; index<64; index++) { + if (sysconf.conf_mmio_addrx[index+8] == 0) { + sysconf.conf_mmio_addr[index+8] = (nodeid & 0x3f) ; + sysconf.conf_mmio_addrx[index+8] = 1 | ((linkn & 0x7)<<4); + return index; + } + } + + return 0; +} + + +void store_conf_io_addr(u32 nodeid, u32 linkn, u32 reg, u32 index, + u32 io_min, u32 io_max) +{ + u32 val; + + /* io range allocation */ + index = (reg-0xc0)>>3; + + val = (nodeid & 0x3f); // 6 bits used + sysconf.conf_io_addr[index] = val | ((io_max<<8) & 0xfffff000); //limit : with nodeid + val = 3 | ((linkn & 0x7)<<4) ; // 8 bits used + sysconf.conf_io_addrx[index] = val | ((io_min<<8) & 0xfffff000); // base : with enable bit + + if (sysconf.io_addr_num < (index+1)) + sysconf.io_addr_num = index+1; +} + + +void store_conf_mmio_addr(u32 nodeid, u32 linkn, u32 reg, u32 index, + u32 mmio_min, u32 mmio_max) +{ + u32 val; + + /* io range allocation */ + index = (reg-0x80)>>3; + + val = (nodeid & 0x3f) ; // 6 bits used + sysconf.conf_mmio_addr[index] = val | (mmio_max & 0xffffff00); //limit : with nodeid and linkn + val = 3 | ((linkn & 0x7)<<4) ; // 8 bits used + sysconf.conf_mmio_addrx[index] = val | (mmio_min & 0xffffff00); // base : with enable bit + + if ( sysconf.mmio_addr_num<(index+1)) + sysconf.mmio_addr_num = index+1; +} + + +void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, + u32 io_min, u32 io_max) +{ + u32 i; + u32 tempreg; + + /* io range allocation */ + tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit + for (i=0; i<sysconf.nodes; i++) + pci_write_config32(__f1_dev[i], reg+4, tempreg); + + tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? +#if 0 + // FIXME: can we use VGA reg instead? + if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { + printk(BIOS_SPEW, "%s, enabling legacy VGA IO forwarding for %s link %s\n", + __func__, dev_path(dev), link); + tempreg |= PCI_IO_BASE_VGA_EN; + } + if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_NO_ISA) { + tempreg |= PCI_IO_BASE_NO_ISA; + } +#endif + for (i=0; i<sysconf.nodes; i++) + pci_write_config32(__f1_dev[i], reg, tempreg); +} + +void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmio_min, u32 mmio_max, u32 nodes) +{ + u32 i; + u32 tempreg; + + /* io range allocation */ + tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit + for (i=0; i<nodes; i++) + pci_write_config32(__f1_dev[i], reg+4, tempreg); + tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); + for (i=0; i<sysconf.nodes; i++) + pci_write_config32(__f1_dev[i], reg, tempreg); +} diff --git a/src/northbridge/amd/amdfam10/ht_config.h b/src/northbridge/amd/amdfam10/ht_config.h new file mode 100644 index 0000000..c2d6c4c --- /dev/null +++ b/src/northbridge/amd/amdfam10/ht_config.h @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +typedef struct amdfam10_sysconf_t sys_info_conf_t; + +/* FIXME */ +u32 amdfam10_nodeid(device_t dev); +extern device_t __f1_dev[]; + +struct dram_base_mask_t { + u32 base; //[47:27] at [28:8] + u32 mask; //[47:27] at [28:8] and enable at bit 0 +}; + +struct dram_base_mask_t get_dram_base_mask(u32 nodeid); + +u32 get_ht_c_index(struct bus *link); +void store_ht_c_conf_bus(struct bus *link); + +void set_config_map_reg(struct bus *link); +void clear_config_map_reg(struct bus *link); + + +void store_conf_io_addr(u32 nodeid, u32 linkn, u32 reg, u32 index, + u32 io_min, u32 io_max); + +void store_conf_mmio_addr(u32 nodeid, u32 linkn, u32 reg, u32 index, + u32 mmio_min, u32 mmio_max); + + +u32 get_io_addr_index(u32 nodeid, u32 linkn); +u32 get_mmio_addr_index(u32 nodeid, u32 linkn); + +void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, + u32 io_min, u32 io_max); + +void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmio_min, u32 mmio_max, u32 nodes); + + diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index f28c01d..409ce0f 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -32,6 +32,7 @@
#include <cpu/x86/lapic.h> #include <cpu/amd/mtrr.h> +#include <cpu/amd/amdfam10_sysconf.h>
#if CONFIG_LOGICAL_CPUS #include <cpu/amd/multicore.h> @@ -39,14 +40,13 @@ #endif
#include "northbridge.h" - #include "amdfam10.h" +#include "ht_config.h"
#if CONFIG_HW_MEM_HOLE_SIZEK != 0 #include <cpu/amd/model_10xxx_rev.h> #endif
-#include <cpu/amd/amdfam10_sysconf.h> #if CONFIG_AMD_SB_CIMX #include <sb_cimx.h> #endif @@ -55,7 +55,7 @@ struct amdfam10_sysconf_t sysconf;
#define FX_DEVS NODE_NUMS static device_t __f0_dev[FX_DEVS]; -static device_t __f1_dev[FX_DEVS]; +device_t __f1_dev[FX_DEVS]; static device_t __f2_dev[FX_DEVS]; static device_t __f4_dev[FX_DEVS]; static unsigned fx_devs=0; @@ -111,7 +111,7 @@ static void f1_write_config32(unsigned reg, u32 value) } }
-static u32 amdfam10_nodeid(device_t dev) +u32 amdfam10_nodeid(device_t dev) { #if NODE_NUMS == 64 unsigned busn; @@ -127,8 +127,6 @@ static u32 amdfam10_nodeid(device_t dev) #endif }
-#include "conf.c" - static void set_vga_enable_reg(u32 nodeid, u32 linkn) { u32 val; @@ -140,177 +138,142 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn)
}
-static bool is_non_coherent_link(struct device *dev, struct bus *link) +#if 0 +static void FIXME_add_more_links(); { - u32 link_type; - do { - link_type = pci_read_config32(dev, link->cap + 0x18); - } while (link_type & ConnectionPending); - - if (!(link_type & LinkConnected)) - return false; - - do { - link_type = pci_read_config32(dev, link->cap + 0x18); - } while (!(link_type & InitComplete)); - - return !!(link_type & NonCoherent); + if (link->link_num > 3) { + u32 regpos; + u32 reg; + regpos = 0x170 + 4 * (link->link_num & 3); // it is only on sublink0 + reg = pci_read_config32(dev, regpos); + if(reg & 1) return max; // already ganged no sblink1 + + dev = get_node_pci(nodeid, 4); + } } +#endif
-static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_sblink, - u32 max) -{ -// I want to put sb chain in bus 0 can I? - +#define HT_ROUTE_SCAN 0 +#define HT_ROUTE_FINAL 1
- int i; - u32 ht_c_index; - u32 ht_unitid_base[4]; // here assume only 4 HT device on chain - u32 max_bus; - u32 min_bus; - u32 busses; - u32 segn = max>>8; -#if CONFIG_SB_HT_CHAIN_ON_BUS0 > 1 - u32 busn = max&0xff; -#endif - u32 max_devfn; +static void ht_route_link(struct bus *link, int mode) +{ +#if 0 + u32 busses;
- if (link->link_num > 3) { - u32 regpos; - u32 reg; - regpos = 0x170 + 4 * (link->link_num & 3); // it is only on sublink0 - reg = pci_read_config32(dev, regpos); - if(reg & 1) return max; // already ganged no sblink1 + if (mode == HT_ROUTE_SCAN) { + if (link->dev->bus->subordinate == 0) + link->secondary = 0; + else + link->secondary = link->dev->bus->subordinate + 1;
- dev = get_node_pci(nodeid, 4); - } + link->subordinate = link->secondary; + }
- /* Check for connected link. */ - link->cap = 0x80 + ((link->link_num & 3) * 0x20); - if (!is_non_coherent_link(dev, link)) - return max; + /* Configure the bus numbers for this bridge: the configuration + * transactions will not be propagated by the bridge if it is + * not correctly configured + */ + busses = pci_read_config32(link->dev, link->cap + 0x14); + busses &= 0xffff00ff; + busses |= ((u32)(link->secondary) << 8); + pci_write_config32(link->dev, link->cap + 0x14, busses); + + if (mode == HT_ROUTE_FINAL) { + if (CONFIG_HT_CHAIN_DISTRIBUTE) + link->dev->bus->subordinate = ALIGN_UP(link->subordinate, 8) - 1; + else + link->dev->bus->subordinate = link->subordinate; + } +#endif +}
+static u32 amdfam10_scan_chain(struct bus *link, u32 max) +{ /* See if there is an available configuration space mapping * register in function 1. */ - ht_c_index = get_ht_c_index(nodeid, link->link_num, &sysconf); - - if(ht_c_index>=4) return max; + if (get_ht_c_index(link) >= 4) + return max;
/* Set up the primary, secondary and subordinate bus numbers. * We have no idea how many busses are behind this bridge yet, * so we set the subordinate bus number to 0xff for the moment. */ -#if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0 - // first chain will on bus 0 - if (is_sblink) { // actually max is 0 here - min_bus = max; - } - #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 1 - // second chain will be on 0x40, third 0x80, forth 0xc0 - // i would refined that to 2, 3, 4 ==> 0, 0x, 40, 0x80, 0xc0 - // >4 will use more segments, We can have 16 segmment and every segment have 256 bus, For that case need the kernel support mmio pci config. - else { - min_bus = ((busn>>3) + 1) << 3; // one node can have 8 link and segn is the same - } - max = min_bus | (segn<<8); - #else - //other ... - else { - min_bus = ++max; - } - #endif -#else - min_bus = ++max; -#endif - max_bus = 0xfc | (segn<<8); - - link->secondary = min_bus; - link->subordinate = max_bus; - - /* Read the existing primary/secondary/subordinate bus - * number configuration. - */ - busses = pci_read_config32(dev, link->cap + 0x14); - - /* Configure the bus numbers for this bridge: the configuration - * transactions will not be propagates by the bridge if it is - * not correctly configured - */ - busses &= 0xffff00ff; - busses |= ((u32)(link->secondary) << 8); - pci_write_config32(dev, link->cap + 0x14, busses);
+ ht_route_link(link, HT_ROUTE_SCAN);
/* set the config map space */ - - set_config_map_reg(nodeid, link->link_num, ht_c_index, link->secondary, link->subordinate, sysconf.segbit, sysconf.nodes); + set_config_map_reg(link);
/* Now we can scan all of the subordinate busses i.e. the * chain on the hypertranport link */ - for(i=0;i<4;i++) { - ht_unitid_base[i] = 0x20; - }
- //if ext conf is enabled, only need use 0x1f - if (min_bus == 0) - max_devfn = (0x17<<3) | 7; - else - max_devfn = (0x1f<<3) | 7; - - max = hypertransport_scan_chain(link, 0, max_devfn, max, ht_unitid_base, offset_unit_id(is_sblink)); + link->subordinate = hypertransport_scan_chain(link, link->secondary);
/* We know the number of busses behind this bridge. Set the * subordinate bus number to it's real value */ - if(ht_c_index>3) { // clear the extend reg - clear_config_map_reg(nodeid, link->link_num, ht_c_index, (max+1)>>sysconf.segbit, (link->subordinate)>>sysconf.segbit, sysconf.nodes); + if (0) { + /* Clear the extend reg. */ + clear_config_map_reg(link); } + ht_route_link(link, HT_ROUTE_FINAL);
- link->subordinate = max; - set_config_map_reg(nodeid, link->link_num, ht_c_index, link->secondary, link->subordinate, sysconf.segbit, sysconf.nodes); - sysconf.ht_c_num++; + set_config_map_reg(link);
- { - // use ht_unitid_base to update hcdn_reg - u32 temp = 0; - for(i=0;i<4;i++) { - temp |= (ht_unitid_base[i] & 0xff) << (i*8); - } - - sysconf.hcdn_reg[ht_c_index] = temp; + store_ht_c_conf_bus(link); + return link->subordinate; +}
+/* Do sb ht chain at first, in case s2885 put sb chain + * (8131/8111) on link2, but put 8151 on link0. + */ +static void relocate_sb_ht_chain(void) +{ + struct device *dev; + struct bus *link, *prev = NULL; + u8 sblink; + + dev = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0)); + sblink = (pci_read_config32(dev, 0x64)>>8) & 7; + link = dev->link_list; + + while (link) { + if (link->link_num == sblink) { + if (!prev) + return; + prev->next = link->next; + link->next = dev->link_list; + dev->link_list = link; + return; } - store_ht_c_conf_bus(nodeid, link->link_num, ht_c_index, link->secondary, link->subordinate, &sysconf); - return max; + prev = link; + link = link->next; + } }
-static unsigned amdfam10_scan_chains(device_t dev, unsigned max) +static void trim_ht_chain(struct device *dev) { - unsigned nodeid; struct bus *link; - unsigned sblink = sysconf.sblk;
- nodeid = amdfam10_nodeid(dev); - - /* Do sb ht chain at first, in case s2885 put sb chain (8131/8111) on link2, but put 8151 on link0 */ + /* Check for connected link. */ for (link = dev->link_list; link; link = link->next) { - bool is_sblink = (nodeid == 0) && (link->link_num == sblink); - if ((CONFIG_SB_HT_CHAIN_ON_BUS0 > 0) && is_sblink) - max = amdfam10_scan_chain(dev, nodeid, link, is_sblink, max); + link->cap = 0x80 + ((link->link_num & 3) * 0x20); + link->ht_link_up = ht_is_non_coherent_link(link); } +}
-#if CONFIG_PCI_BUS_SEGN_BITS - max = check_segn(dev, max, sysconf.nodes, &sysconf); -#endif +static unsigned amdfam10_scan_chains(device_t dev, unsigned max) +{ + struct bus *link;
- for (link = dev->link_list; link; link = link->next) { - bool is_sblink = (nodeid == 0) && (link->link_num == sblink); - if ((CONFIG_SB_HT_CHAIN_ON_BUS0 > 0) && is_sblink) - continue; + trim_ht_chain(dev);
- max = amdfam10_scan_chain(dev, nodeid, link, is_sblink, max); + for (link = dev->link_list; link; link = link->next) { + if (link->ht_link_up) + max = amdfam10_scan_chain(link, max); } return max; } @@ -599,9 +562,15 @@ static const struct pci_driver mcf0_driver __pci_driver = { .device = 0x1200, };
+static void amdfam10_nb_init(void *chip_info) +{ + relocate_sb_ht_chain(); +} + struct chip_operations northbridge_amd_amdfam10_ops = { CHIP_NAME("AMD FAM10 Northbridge") .enable_dev = 0, + .init = amdfam10_nb_init, };
static void amdfam10_domain_read_resources(device_t dev) @@ -739,87 +708,6 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) return mem_hole; }
-// WHY this check? CONFIG_AMDMCT is enabled on all Fam10 boards. -// Does it make sense not to? -#if !CONFIG_AMDMCT -static void disable_hoist_memory(unsigned long hole_startk, int node_id) -{ - int i; - device_t dev; - struct dram_base_mask_t d; - u32 sel_m; - u32 sel_hi_en; - u32 hoist; - u32 hole_sizek; - - u32 one_DCT; - struct sys_info *sysinfox = (struct sys_info *)((CONFIG_RAMTOP) - sizeof(*sysinfox)); // in RAM - struct mem_info *meminfo; - meminfo = &sysinfox->meminfo[node_id]; - - one_DCT = get_one_DCT(meminfo); - - // 1. find which node has hole - // 2. change limit in that node. - // 3. change base and limit in later node - // 4. clear that node f0 - - // if there is not mem hole enabled, we need to change it's base instead - - hole_sizek = (4*1024*1024) - hole_startk; - - for(i=NODE_NUMS-1;i>node_id;i--) { - - d = get_dram_base_mask(i); - - if(!(d.mask & 1)) continue; - - d.base -= (hole_sizek>>9); - d.mask -= (hole_sizek>>9); - set_dram_base_mask(i, d, sysconf.nodes); - - if(get_DctSelHiEn(i) & 1) { - sel_m = get_DctSelBaseAddr(i); - sel_m -= hole_startk>>10; - set_DctSelBaseAddr(i, sel_m); - } - } - - d = get_dram_base_mask(node_id); - dev = __f1_dev[node_id]; - sel_hi_en = get_DctSelHiEn(node_id); - - if(sel_hi_en & 1) { - sel_m = get_DctSelBaseAddr(node_id); - } - hoist = pci_read_config32(dev, 0xf0); - if(hoist & 1) { - pci_write_config32(dev, 0xf0, 0); - d.mask -= (hole_sizek>>9); - set_dram_base_mask(node_id, d, sysconf.nodes); - if(one_DCT || (sel_m >= (hole_startk>>10))) { - if(sel_hi_en & 1) { - sel_m -= hole_startk>>10; - set_DctSelBaseAddr(node_id, sel_m); - } - } - if(sel_hi_en & 1) { - set_DctSelBaseOffset(node_id, 0); - } - } else { - d.base -= (hole_sizek>>9); - d.mask -= (hole_sizek>>9); - set_dram_base_mask(node_id, d, sysconf.nodes); - - if(sel_hi_en & 1) { - sel_m -= hole_startk>>10; - set_DctSelBaseAddr(node_id, sel_m); - } - } - -} -#endif - #endif
#include <cbmem.h> @@ -947,44 +835,6 @@ static void amdfam10_domain_set_resources(device_t dev) reset_memhole = 0; }
- #if !CONFIG_AMDMCT - //mmio_basek = 3*1024*1024; // for debug to meet boundary - - if(reset_memhole) { - if(mem_hole.node_id!=-1) { - /* We need to select CONFIG_HW_MEM_HOLE_SIZEK for raminit, it can not - make hole_startk to some basek too! - We need to reset our Mem Hole, because We want more big HOLE - than we already set - Before that We need to disable mem hole at first, becase - memhole could already be set on i+1 instead - */ - disable_hoist_memory(mem_hole.hole_startk, mem_hole.node_id); - } - - #if CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC - // We need to double check if the mmio_basek is valid for hole - // setting, if it is equal to basek, we need to decrease it some - resource_t basek_pri; - for (i = 0; i < sysconf.nodes; i++) { - struct dram_base_mask_t d; - resource_t basek; - d = get_dram_base_mask(i); - - if(!(d.mask &1)) continue; - - basek = ((resource_t)(d.base & 0x1fffff00)) << 9; - if(mmio_basek == (u32)basek) { - mmio_basek -= (uin32_t)(basek - basek_pri); // increase mem hole size to make sure it is on middle of pri node - break; - } - basek_pri = basek; - } - #endif - } - #endif - - #endif
idx = 0x10; @@ -1021,17 +871,6 @@ static void amdfam10_domain_set_resources(device_t dev) if (!ramtop) ramtop = mmio_basek * 1024; } - #if !CONFIG_AMDMCT - #if CONFIG_HW_MEM_HOLE_SIZEK != 0 - if(reset_memhole) { - struct sys_info *sysinfox = (struct sys_info *)((CONFIG_RAMTOP) - sizeof(*sysinfox)); // in RAM - struct mem_info *meminfo; - meminfo = &sysinfox->meminfo[i]; - sizek += hoist_memory(mmio_basek,i, get_one_DCT(meminfo), sysconf.nodes); - } - #endif - #endif - basek = mmio_basek; } if ((basek + sizek) <= 4*1024*1024) { @@ -1157,14 +996,16 @@ static void sysconf_init(device_t dev) // first node static void add_more_links(device_t dev, unsigned total_links) { struct bus *link, *last = NULL; - int link_num; + int link_num = -1;
- for (link = dev->link_list; link; link = link->next) + for (link = dev->link_list; link; link = link->next) { + if (link_num < link->link_num) + link_num = link->link_num; last = link; + }
if (last) { - int links = total_links - last->link_num; - link_num = last->link_num; + int links = total_links - (link_num + 1); if (links > 0) { link = malloc(links*sizeof(*link)); if (!link) @@ -1174,7 +1015,6 @@ static void add_more_links(device_t dev, unsigned total_links) } } else { - link_num = -1; link = malloc(total_links*sizeof(*link)); memset(link, 0, total_links*sizeof(*link)); dev->link_list = link; diff --git a/src/northbridge/amd/amdk8/Kconfig b/src/northbridge/amd/amdk8/Kconfig index 65dc173..6096ab5 100644 --- a/src/northbridge/amd/amdk8/Kconfig +++ b/src/northbridge/amd/amdk8/Kconfig @@ -65,6 +65,9 @@ config SB_HT_CHAIN_UNITID_OFFSET_ONLY bool default n
+config HT_CHAIN_DISTRIBUTE + def_bool n + config QRANK_DIMM_SUPPORT bool default n diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index a0c3d7f..9f6ccbd 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -79,37 +79,65 @@ static void f1_write_config32(unsigned reg, u32 value) } }
+#define HT_ROUTE_SCAN 0 +#define HT_ROUTE_FINAL 1 + +static void ht_route_link(struct bus *link, int mode) +{ +#if 0 + u32 busses; + + if (mode == HT_ROUTE_SCAN) { + if (link->dev->bus->subordinate == 0) + link->secondary = 0; + else + link->secondary = link->dev->bus->subordinate + 1; + + link->subordinate = link->secondary; + } + + /* Configure the bus numbers for this bridge: the configuration + * transactions will not be propagated by the bridge if it is + * not correctly configured + */ + busses = pci_read_config32(link->dev, link->cap + 0x14); + busses &= 0xff000000; + busses |= link->dev->bus->secondary & 0xff; + if (mode == HT_ROUTE_CLOSE) { + busses |= 0xfeff << 8; + } else if (mode == HT_ROUTE_SCAN) { + busses |= ((u32) link->secondary & 0xff) << 8; + busses |= 0xff << 16; /* MAX PCI_BUS number here */ + } else if (mode == HT_ROUTE_FINAL) { + busses |= ((u32) link->secondary & 0xff) << 8; + busses |= ((u32) link->subordinate & 0xff) << 16; + } + + pci_write_config32(link->dev, link->cap + 0x14, busses); + + if (mode == HT_ROUTE_FINAL) { + /* Second chain will be on 0x40, third 0x80, forth 0xc0. */ + if (CONFIG_HT_CHAIN_DISTRIBUTE) + link->dev->bus->subordinate = ALIGN_UP(link->subordinate, 0x40) - 1; + else + link->dev->bus->subordinate = link->subordinate; + } +#endif +} + static u32 amdk8_nodeid(device_t dev) { return (dev->path.pci.devfn >> 3) - 0x18; }
-static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_sblink, - u32 max) +static u32 amdk8_scan_chain(struct bus *link, u32 max) { - - u32 link_type; - int i; - u32 busses, config_busses; + int index; + u32 config_busses; u32 free_reg, config_reg; - u32 ht_unitid_base[4]; // here assume only 4 HT device on chain - u32 max_bus; - u32 min_bus; - u32 max_devfn;
- link->cap = 0x80 + (link->link_num * 0x20); - do { - link_type = pci_read_config32(dev, link->cap + 0x18); - } while(link_type & ConnectionPending); - if (!(link_type & LinkConnected)) { - return max; - } - do { - link_type = pci_read_config32(dev, link->cap + 0x18); - } while(!(link_type & InitComplete)); - if (!(link_type & NonCoherent)) { - return max; - } + u32 nodeid = amdk8_nodeid(link->dev); + /* See if there is an available configuration space mapping * register in function 1. */ @@ -141,47 +169,10 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_ * We have no idea how many busses are behind this bridge yet, * so we set the subordinate bus number to 0xff for the moment. */ -#if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0 - // first chain will on bus 0 - if(is_sblink) { // actually max is 0 here - min_bus = max; - } - #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 1 - // second chain will be on 0x40, third 0x80, forth 0xc0 - else { - min_bus = ((max>>6) + 1) * 0x40; - } - max = min_bus; - #else - //other ... - else { - min_bus = ++max; - } - #endif -#else - min_bus = ++max; -#endif - max_bus = 0xff;
- link->secondary = min_bus; - link->subordinate = max_bus; + ht_route_link(link, HT_ROUTE_SCAN);
- /* Read the existing primary/secondary/subordinate bus - * number configuration. - */ - busses = pci_read_config32(dev, link->cap + 0x14); config_busses = f1_read_config32(config_reg); - - /* Configure the bus numbers for this bridge: the configuration - * transactions will not be propagates by the bridge if it is - * not correctly configured - */ - busses &= 0xff000000; - busses |= (((unsigned int)(dev->bus->secondary) << 0) | - ((unsigned int)(link->secondary) << 8) | - ((unsigned int)(link->subordinate) << 16)); - pci_write_config32(dev, link->cap + 0x14, busses); - config_busses &= 0x000fc88; config_busses |= (3 << 0) | /* rw enable, no device compare */ @@ -194,67 +185,71 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_ /* Now we can scan all of the subordinate busses i.e. the * chain on the hypertranport link */ - for(i=0;i<4;i++) { - ht_unitid_base[i] = 0x20; - } - - if (min_bus == 0) - max_devfn = (0x17<<3) | 7; - else - max_devfn = (0x1f<<3) | 7; - - max = hypertransport_scan_chain(link, 0, max_devfn, max, ht_unitid_base, offset_unit_id(is_sblink)); + link->subordinate = hypertransport_scan_chain(link, link->secondary);
/* We know the number of busses behind this bridge. Set the * subordinate bus number to it's real value */ - link->subordinate = max; - busses = (busses & 0xff00ffff) | - ((unsigned int) (link->subordinate) << 16); - pci_write_config32(dev, link->cap + 0x14, busses); + + ht_route_link(link, HT_ROUTE_FINAL);
config_busses = (config_busses & 0x00ffffff) | (link->subordinate << 24); f1_write_config32(config_reg, config_busses);
- { - // use config_reg and ht_unitid_base to update hcdn_reg - int index; - u32 temp = 0; - index = (config_reg-0xe0) >> 2; - for(i=0;i<4;i++) { - temp |= (ht_unitid_base[i] & 0xff) << (i*8); - } + index = (config_reg-0xe0) >> 2; + sysconf.hcdn_reg[index] = link->hcdn_reg;
- sysconf.hcdn_reg[index] = temp; + return link->subordinate; +}
+/* Do sb ht chain at first, in case s2885 put sb chain + * (8131/8111) on link2, but put 8151 on link0. + */ +static void relocate_sb_ht_chain(void) +{ + struct device *dev; + struct bus *link, *prev = NULL; + u8 sblink; + + dev = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0)); + sblink = (pci_read_config32(dev, 0x64)>>8) & 3; + link = dev->link_list; + + while (link) { + if (link->link_num == sblink) { + if (!prev) + return; + prev->next = link->next; + link->next = dev->link_list; + dev->link_list = link; + return; } - return max; + prev = link; + link = link->next; + } }
-static unsigned amdk8_scan_chains(device_t dev, unsigned max) +static void trim_ht_chain(struct device *dev) { - unsigned nodeid; struct bus *link; - unsigned sblink = 0;
- nodeid = amdk8_nodeid(dev); - if (nodeid == 0) - sblink = (pci_read_config32(dev, 0x64)>>8) & 3; - - // do sb ht chain at first, in case s2885 put sb chain (8131/8111) on link2, but put 8151 on link0 + /* Check for connected links. */ for (link = dev->link_list; link; link = link->next) { - bool is_sblink = (nodeid == 0) && (link->link_num == sblink); - if ((CONFIG_SB_HT_CHAIN_ON_BUS0 > 0) && is_sblink) - max = amdk8_scan_chain(dev, nodeid, link, is_sblink, max); + link->cap = 0x80 + (link->link_num * 0x20); + link->ht_link_up = ht_is_non_coherent_link(link); } +}
- for (link = dev->link_list; link; link = link->next) { - bool is_sblink = (nodeid == 0) && (link->link_num == sblink); - if ((CONFIG_SB_HT_CHAIN_ON_BUS0 > 0) && is_sblink) - continue; +static unsigned amdk8_scan_chains(device_t dev, unsigned max) +{ + struct bus *link;
- max = amdk8_scan_chain(dev, nodeid, link, is_sblink, max); + trim_ht_chain(dev); + + for (link = dev->link_list; link; link = link->next) { + if (link->ht_link_up) + max = amdk8_scan_chain(link, max); } return max; } @@ -625,9 +620,15 @@ static const struct pci_driver mcf0_driver __pci_driver = { .device = 0x1100, };
+static void amdk8_nb_init(void *chip_info) +{ + relocate_sb_ht_chain(); +} + struct chip_operations northbridge_amd_amdk8_ops = { CHIP_NAME("AMD K8 Northbridge") .enable_dev = 0, + .init = amdk8_nb_init, };
static void amdk8_domain_read_resources(device_t dev) @@ -1159,14 +1160,16 @@ static struct device_operations pci_domain_ops = { static void add_more_links(device_t dev, unsigned total_links) { struct bus *link, *last = NULL; - int link_num; + int link_num = -1;
- for (link = dev->link_list; link; link = link->next) + for (link = dev->link_list; link; link = link->next) { + if (link_num < link->link_num) + link_num = link->link_num; last = link; + }
if (last) { - int links = total_links - last->link_num; - link_num = last->link_num; + int links = total_links - (link_num + 1); if (links > 0) { link = malloc(links*sizeof(*link)); if (!link) @@ -1176,7 +1179,6 @@ static void add_more_links(device_t dev, unsigned total_links) } } else { - link_num = -1; link = malloc(total_links*sizeof(*link)); memset(link, 0, total_links*sizeof(*link)); dev->link_list = link;
-
Kyösti Mälkki