Attention is currently required from: Paul Menzel, YH Lin. Kevin Chang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59973 )
Change subject: mb/google/brya/var/taeko: Fix PLD group order (W/A) ......................................................................
Patch Set 6:
(6 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59973/comment/50c64307_7d4e3b99 PS5, Line 7: (W/A)
What does W/A emean?
This is mean workaround.
https://review.coreboot.org/c/coreboot/+/59973/comment/b6c9c86d_a5301283 PS5, Line 7: order(W/A)
Please add a space before (.
Updated in latest patch.
https://review.coreboot.org/c/coreboot/+/59973/comment/461e3043_448a5b25 PS5, Line 9: table(667471b8d807da5a5a9277db47e069ad3b1351c7)
Please add a space before (.
Updated in latest patch.
https://review.coreboot.org/c/coreboot/+/59973/comment/92df4b4b_2d7ac627 PS5, Line 9: In ec/google/chromeec: Add PLD to EC conn in ACPI table(667471b8d807da5a5a9277db47e069ad3b1351c7), PLD is added to ACPI table. It causes the DUT to not boot into the OS. So fix the USB3/USB2 Type-C Port C2 PLD group order from 3 to 2 to solve this issue.
Please reflow for 75 characters per line.
Updated in latest patch.
https://review.coreboot.org/c/coreboot/+/59973/comment/a05dfbe7_3cd724fc PS5, Line 9: In ec/google/chromeec: Add PLD to EC conn in ACPI table(667471b8d807da5a5a9277db47e069ad3b1351c7)
In commit 667471b8d8 (ec/google/chromeec: Add PLD to EC conn in ACPI table) …
Updated in latest patch.
https://review.coreboot.org/c/coreboot/+/59973/comment/ebaec3e2_17004b3c PS5, Line 10:
Fixes: 667471b8d8 ("ec/google/chromeec: Add PLD to EC conn in ACPI table")
Updated in latest patch.
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Kevin Chang (Code Review)