Bora Guvendik has uploaded this change for review. ( https://review.coreboot.org/25802
Change subject: [WIP] soc/intel/apollolake: Use bootblock common stage ......................................................................
[WIP] soc/intel/apollolake: Use bootblock common stage
Change apollolake bootcode to use common bootblock stage
Change-Id: I319453c902632f26eec63ab9c1e9bb6956b466fb Signed-off-by: Bora Guvendik bora.guvendik@intel.com --- M src/soc/intel/apollolake/Kconfig M src/soc/intel/apollolake/Makefile.inc A src/soc/intel/apollolake/bootblock/cpu.c R src/soc/intel/apollolake/bootblock/pch.c A src/soc/intel/apollolake/include/soc/pch.h 5 files changed, 63 insertions(+), 23 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/25802/1
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index a9b90c4..a5842ec 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -66,6 +66,8 @@ select SA_ENABLE_IMR select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE + select SOC_INTEL_COMMON_BASECODE + select SOC_INTEL_COMMON_BASECODE_BOOTBLOCK select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_ACPI select SOC_INTEL_COMMON_BLOCK_CPU diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 65df559..854f328 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -8,7 +8,8 @@ subdirs-y += ../../../cpu/x86/tsc subdirs-y += ../../../cpu/x86/cache
-bootblock-y += bootblock/bootblock.c +bootblock-y += bootblock/cpu.c +bootblock-y += bootblock/pch.c bootblock-y += car.c bootblock-y += heci.c bootblock-y += gspi.c diff --git a/src/soc/intel/apollolake/bootblock/cpu.c b/src/soc/intel/apollolake/bootblock/cpu.c new file mode 100644 index 0000000..9568750 --- /dev/null +++ b/src/soc/intel/apollolake/bootblock/cpu.c @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * (Written by Andrey Petrov andrey.petrov@intel.com for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <intelbasecode/bootblock.h> +#include <intelblocks/fast_spi.h> + +void bootblock_cpu_init(void) +{ + fast_spi_early_init(PRERAM_SPI_BASE_ADDRESS); + fast_spi_cache_bios_region(); +} diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/pch.c similarity index 84% rename from src/soc/intel/apollolake/bootblock/bootblock.c rename to src/soc/intel/apollolake/bootblock/pch.c index 63b023d..4a4e793 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/pch.c @@ -15,23 +15,18 @@ * GNU General Public License for more details. */ #include <arch/cpu.h> +#include <intelbasecode/bootblock.h> #include <bootblock_common.h> #include <device/pci.h> #include <intelblocks/cpulib.h> -#include <intelblocks/fast_spi.h> #include <intelblocks/pcr.h> #include <intelblocks/rtc.h> -#include <intelblocks/systemagent.h> #include <intelblocks/pmclib.h> #include <soc/iomap.h> -#include <soc/cpu.h> #include <soc/gpio.h> -#include <soc/systemagent.h> +#include <soc/uart.h> #include <soc/pci_devs.h> #include <soc/pm.h> -#include <soc/uart.h> -#include <spi-generic.h> -#include <timestamp.h>
static const struct pad_config tpm_spi_configs[] = { #if IS_ENABLED(CONFIG_SOC_INTEL_GLK) @@ -47,12 +42,10 @@ gpio_configure_pads(tpm_spi_configs, ARRAY_SIZE(tpm_spi_configs)); }
-asmlinkage void bootblock_c_entry(uint64_t base_timestamp) +static void enable_p2sbbar(void) { device_t dev;
- bootblock_systemagent_early_init(); - dev = PCH_DEV_P2SB; /* BAR and MMIO enable for PCR-Space, so that GPIOs can be configured */ pci_write_config32(dev, PCI_BASE_ADDRESS_0, CONFIG_PCR_BASE_ADDRESS); @@ -65,11 +58,6 @@ pci_write_config16(dev, PCI_BASE_ADDRESS_4, ACPI_BASE_ADDRESS); pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MASTER); - - enable_rtc_upper_bank(); - - /* Call lib/bootblock.c main */ - bootblock_main_with_timestamp(base_timestamp); }
static void enable_pmcbar(void) @@ -87,28 +75,30 @@ PCI_COMMAND_MASTER); }
-void bootblock_soc_early_init(void) +void bootblock_pch_early_init(void) { - uint32_t reg; + enable_p2sbbar(); + + enable_rtc_upper_bank();
enable_pmcbar();
/* Clear global reset promotion bit */ pmc_global_reset_enable(0);
- /* Prepare UART for serial console. */ if (IS_ENABLED(CONFIG_SOC_UART_DEBUG)) pch_uart_init(); +} + +void bootblock_pch_init(void) +{ + uint32_t reg;
if (IS_ENABLED(CONFIG_TPM_ON_FAST_SPI)) tpm_enable();
enable_pm_timer_emulation();
- fast_spi_early_init(PRERAM_SPI_BASE_ADDRESS); - - fast_spi_cache_bios_region(); - /* Initialize GPE for use as interrupt status */ pmc_gpe_init();
diff --git a/src/soc/intel/apollolake/include/soc/pch.h b/src/soc/intel/apollolake/include/soc/pch.h new file mode 100644 index 0000000..901f66e --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/pch.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_CANNONLAKE_PCH_H_ +#define _SOC_CANNONLAKE_PCH_H_ + +void pch_uart_init(void); + +#endif