[L] Change in coreboot[main]: [WIP] mb/hardkernel/odroid-h4: add initial odroid-h4 support

[David Milosevic (Code Review)]

Attention is currently required from: Alicja Michalska, Angel Pons.

David Milosevic has posted comments on this change by David Milosevic. ( https://review.coreboot.org/c/coreboot/+/83979?usp=email )

Change subject: [WIP] mb/hardkernel/odroid-h4: add initial odroid-h4 support
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Patch Set 3:

(6 comments)

File src/mainboard/hardkernel/odroid-h4/devicetree.cb:

https://review.coreboot.org/c/coreboot/+/83979/comment/e66059a0_694aa326?usp... :
PS2, Line 17: 	register "s0ix_enable" = "1"
> It's unlikely that you'll get s0ix working with IT8613E unfortunately. […]

Done

https://review.coreboot.org/c/coreboot/+/83979/comment/f4f98129_ecd6425f?usp... :
PS2, Line 84: 		#		.clk_src = 2,
> Nice, schematics are also available from the Odroid wiki: https://wiki.odroid. […]

Thanks for your help, Alicja :)

https://review.coreboot.org/c/coreboot/+/83979/comment/ba25d755_60f3badf?usp... :
PS2, Line 82: #device ref pcie_rp3 on
            : 		#	register "pch_pcie_rp[PCH_RP(3)]" = "{
            : 		#		.clk_src = 2,
            : 		#		.clk_req = 2,
            : 		#		.flags = PCIE_RP_CLK_REQ_DETECT,
            : 		#	}"
            : 		#	smbios_slot_desc	"SlotTypeM2Socket3" "SlotLengthOther"
            : 		#				"M.2/M 2280 (M2_SSD1)" "SlotDataBusWidth2X"
            : 		#end
            : 		#device ref pcie_rp7 on	# LAN1
            : 		#	register "pch_pcie_rp[PCH_RP(7)]" = "{
            : 		#		.clk_src = 3,
            : 		#		.clk_req = 3,
            : 		#		.flags = PCIE_RP_CLK_REQ_DETECT,
            : 		#	}"
            : 		#end
            : 		#device ref pcie_rp9 on	# LAN2
            : 		#	register "pch_pcie_rp[PCH_RP(9)]" = "{
            : 		#		.clk_src = 0,
            : 		#		.clk_req = 0,
            : 		#		.flags = PCIE_RP_CLK_REQ_DETECT,
            : 		#	}"
            : 		#end
            : 		#device ref pcie_rp10 on
            : 		#	register "pch_pcie_rp[PCH_RP(10)]" = "{
            : 		#		.clk_src = 1,
            : 		#		.clk_req = 1,
            : 		#		.flags = PCIE_RP_CLK_REQ_DETECT,
            : 		#	}"
            : 		#	smbios_slot_desc	"SlotTypeM2Socket1_SD" "SlotLengthOther"
            : 		#				"M.2/E 2230 (M2_WIFI1)" "SlotDataBusWidth1X"
            : 		#end
> I've left it commented out so that the differences are easier to see, but you should obviously uncom […]

Hi and thanks for your help, Angel :)

We already had something similar for the NVME but did not update this patch yet:

```
                device ref pcie_rp9 on
                        register "pch_pcie_rp[PCH_RP(9)]" = "{
                                .flags = PCIE_RP_LTR | PCIE_RP_AER,
                                .clk_src = 0,
                                .clk_req = 0,
                                .pcie_rp_aspm = ASPM_DISABLE,
                        }"
                end
```

I am going to give your proposal a try and hopefully it will fix our NVME issue. Thanks again.

https://review.coreboot.org/c/coreboot/+/83979/comment/033eb9fc_661bdb7c?usp... :
PS2, Line 141: 				device pnp 2e.6 on end # Mouse
> From what I can see, this board doesn't have PS/2 ports. […]

Done

https://review.coreboot.org/c/coreboot/+/83979/comment/cd2038c1_60e7ea61?usp... :
PS2, Line 148: 				device pnp 2e.a on end # CIR
> CIR seems unused as well

Done

https://review.coreboot.org/c/coreboot/+/83979/comment/fbcfdd38_3635b293?usp... :
PS2, Line 156: 	device ref gspi0 on
             : 			register "serial_io_gspi_mode" = "{
             : 				[PchSerialIoIndexGSPI0] = PchSerialIoPci,
             : 			}"
             : 		end
> GSPI0 pins are disconnected in the schematic, this can be disabled.

Done