Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46763 )
Change subject: soc/intel/broadwell/pch: Use common PCIe ACPI code ......................................................................
soc/intel/broadwell/pch: Use common PCIe ACPI code
Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 does not change.
Change-Id: I1f41ce943e25dceab79c7d7ee2ed797c392dcd52 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/soc/intel/broadwell/pch/acpi/pch.asl D src/soc/intel/broadwell/pch/acpi/pcie.asl D src/soc/intel/broadwell/pch/acpi/pcie_port.asl 3 files changed, 1 insertion(+), 214 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/46763/1
diff --git a/src/soc/intel/broadwell/pch/acpi/pch.asl b/src/soc/intel/broadwell/pch/acpi/pch.asl index 5a94bca..7b57859 100644 --- a/src/soc/intel/broadwell/pch/acpi/pch.asl +++ b/src/soc/intel/broadwell/pch/acpi/pch.asl @@ -45,7 +45,7 @@ #include "adsp.asl"
// PCI Express Ports 0:1c.x -#include "pcie.asl" +#include <southbridge/intel/common/acpi/pcie.asl>
// USB EHCI 0:1d.0 #include "ehci.asl" diff --git a/src/soc/intel/broadwell/pch/acpi/pcie.asl b/src/soc/intel/broadwell/pch/acpi/pcie.asl deleted file mode 100644 index 72993f93..0000000 --- a/src/soc/intel/broadwell/pch/acpi/pcie.asl +++ /dev/null @@ -1,196 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* Intel PCH PCIe support */ - -Method (IRQM, 1, Serialized) { - - /* Interrupt Map INTA->INTA, INTB->INTB, INTC->INTC, INTD->INTD */ - Name (IQAA, Package() { - Package() { 0x0000ffff, 0, 0, 16 }, - Package() { 0x0000ffff, 1, 0, 17 }, - Package() { 0x0000ffff, 2, 0, 18 }, - Package() { 0x0000ffff, 3, 0, 19 } }) - Name (IQAP, Package() { - Package() { 0x0000ffff, 0, _SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0000ffff, 1, _SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0000ffff, 2, _SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0000ffff, 3, _SB.PCI0.LPCB.LNKD, 0 } }) - - /* Interrupt Map INTA->INTB, INTB->INTC, INTC->INTD, INTD->INTA */ - Name (IQBA, Package() { - Package() { 0x0000ffff, 0, 0, 17 }, - Package() { 0x0000ffff, 1, 0, 18 }, - Package() { 0x0000ffff, 2, 0, 19 }, - Package() { 0x0000ffff, 3, 0, 16 } }) - Name (IQBP, Package() { - Package() { 0x0000ffff, 0, _SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0000ffff, 1, _SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0000ffff, 2, _SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x0000ffff, 3, _SB.PCI0.LPCB.LNKA, 0 } }) - - /* Interrupt Map INTA->INTC, INTB->INTD, INTC->INTA, INTD->INTB */ - Name (IQCA, Package() { - Package() { 0x0000ffff, 0, 0, 18 }, - Package() { 0x0000ffff, 1, 0, 19 }, - Package() { 0x0000ffff, 2, 0, 16 }, - Package() { 0x0000ffff, 3, 0, 17 } }) - Name (IQCP, Package() { - Package() { 0x0000ffff, 0, _SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0000ffff, 1, _SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x0000ffff, 2, _SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0000ffff, 3, _SB.PCI0.LPCB.LNKB, 0 } }) - - /* Interrupt Map INTA->INTD, INTB->INTA, INTC->INTB, INTD->INTC */ - Name (IQDA, Package() { - Package() { 0x0000ffff, 0, 0, 19 }, - Package() { 0x0000ffff, 1, 0, 16 }, - Package() { 0x0000ffff, 2, 0, 17 }, - Package() { 0x0000ffff, 3, 0, 18 } }) - Name (IQDP, Package() { - Package() { 0x0000ffff, 0, _SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x0000ffff, 1, _SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0000ffff, 2, _SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0000ffff, 3, _SB.PCI0.LPCB.LNKC, 0 } }) - - Switch (ToInteger (Arg0)) { - /* PCIe Root Port 1 and 5 */ - Case (Package() { 1, 5 }) { - If (PICM) { - Return (IQAA) - } Else { - Return (IQAP) - } - } - - /* PCIe Root Port 2 and 6 */ - Case (Package() { 2, 6 }) { - If (PICM) { - Return (IQBA) - } Else { - Return (IQBP) - } - } - - /* PCIe Root Port 3 and 7 */ - Case (Package() { 3, 7 }) { - If (PICM) { - Return (IQCA) - } Else { - Return (IQCP) - } - } - - /* PCIe Root Port 4 and 8 */ - Case (Package() { 4, 8 }) { - If (PICM) { - Return (IQDA) - } Else { - Return (IQDP) - } - } - - Default { - If (PICM) { - Return (IQDA) - } Else { - Return (IQDP) - } - } - } -} - -Device (RP01) -{ - Name (_ADR, 0x001c0000) - - #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP02) -{ - Name (_ADR, 0x001c0001) - - #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP03) -{ - Name (_ADR, 0x001c0002) - - #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP04) -{ - Name (_ADR, 0x001c0003) - - #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP05) -{ - Name (_ADR, 0x001c0004) - - #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP06) -{ - Name (_ADR, 0x001c0005) - - #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP07) -{ - Name (_ADR, 0x001c0006) - - #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP08) -{ - Name (_ADR, 0x001c0007) - - #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} diff --git a/src/soc/intel/broadwell/pch/acpi/pcie_port.asl b/src/soc/intel/broadwell/pch/acpi/pcie_port.asl deleted file mode 100644 index 988c817..0000000 --- a/src/soc/intel/broadwell/pch/acpi/pcie_port.asl +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* Included in each PCIe Root Port device */ - -OperationRegion (RPCS, PCI_Config, 0x00, 0xFF) -Field (RPCS, AnyAcc, NoLock, Preserve) -{ - Offset (0x4c), // Link Capabilities - , 24, - RPPN, 8, // Root Port Number - Offset (0x5A), - , 3, - PDC, 1, - Offset (0xDF), - , 6, - HPCS, 1, -}
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46763 )
Change subject: soc/intel/broadwell/pch: Use common PCIe ACPI code ......................................................................
Patch Set 10: Code-Review+1
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46763 )
Change subject: soc/intel/broadwell/pch: Use common PCIe ACPI code ......................................................................
Patch Set 10: Code-Review+2
Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46763 )
Change subject: soc/intel/broadwell/pch: Use common PCIe ACPI code ......................................................................
soc/intel/broadwell/pch: Use common PCIe ACPI code
Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 does not change.
Change-Id: I1f41ce943e25dceab79c7d7ee2ed797c392dcd52 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/46763 Reviewed-by: Michael Niewöhner foss@mniewoehner.de Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/broadwell/pch/acpi/pch.asl D src/soc/intel/broadwell/pch/acpi/pcie.asl D src/soc/intel/broadwell/pch/acpi/pcie_port.asl 3 files changed, 1 insertion(+), 214 deletions(-)
Approvals: build bot (Jenkins): Verified Michael Niewöhner: Looks good to me, approved
diff --git a/src/soc/intel/broadwell/pch/acpi/pch.asl b/src/soc/intel/broadwell/pch/acpi/pch.asl index 5a94bca..7b57859 100644 --- a/src/soc/intel/broadwell/pch/acpi/pch.asl +++ b/src/soc/intel/broadwell/pch/acpi/pch.asl @@ -45,7 +45,7 @@ #include "adsp.asl"
// PCI Express Ports 0:1c.x -#include "pcie.asl" +#include <southbridge/intel/common/acpi/pcie.asl>
// USB EHCI 0:1d.0 #include "ehci.asl" diff --git a/src/soc/intel/broadwell/pch/acpi/pcie.asl b/src/soc/intel/broadwell/pch/acpi/pcie.asl deleted file mode 100644 index 72993f93..0000000 --- a/src/soc/intel/broadwell/pch/acpi/pcie.asl +++ /dev/null @@ -1,196 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* Intel PCH PCIe support */ - -Method (IRQM, 1, Serialized) { - - /* Interrupt Map INTA->INTA, INTB->INTB, INTC->INTC, INTD->INTD */ - Name (IQAA, Package() { - Package() { 0x0000ffff, 0, 0, 16 }, - Package() { 0x0000ffff, 1, 0, 17 }, - Package() { 0x0000ffff, 2, 0, 18 }, - Package() { 0x0000ffff, 3, 0, 19 } }) - Name (IQAP, Package() { - Package() { 0x0000ffff, 0, _SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0000ffff, 1, _SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0000ffff, 2, _SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0000ffff, 3, _SB.PCI0.LPCB.LNKD, 0 } }) - - /* Interrupt Map INTA->INTB, INTB->INTC, INTC->INTD, INTD->INTA */ - Name (IQBA, Package() { - Package() { 0x0000ffff, 0, 0, 17 }, - Package() { 0x0000ffff, 1, 0, 18 }, - Package() { 0x0000ffff, 2, 0, 19 }, - Package() { 0x0000ffff, 3, 0, 16 } }) - Name (IQBP, Package() { - Package() { 0x0000ffff, 0, _SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0000ffff, 1, _SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0000ffff, 2, _SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x0000ffff, 3, _SB.PCI0.LPCB.LNKA, 0 } }) - - /* Interrupt Map INTA->INTC, INTB->INTD, INTC->INTA, INTD->INTB */ - Name (IQCA, Package() { - Package() { 0x0000ffff, 0, 0, 18 }, - Package() { 0x0000ffff, 1, 0, 19 }, - Package() { 0x0000ffff, 2, 0, 16 }, - Package() { 0x0000ffff, 3, 0, 17 } }) - Name (IQCP, Package() { - Package() { 0x0000ffff, 0, _SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0000ffff, 1, _SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x0000ffff, 2, _SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0000ffff, 3, _SB.PCI0.LPCB.LNKB, 0 } }) - - /* Interrupt Map INTA->INTD, INTB->INTA, INTC->INTB, INTD->INTC */ - Name (IQDA, Package() { - Package() { 0x0000ffff, 0, 0, 19 }, - Package() { 0x0000ffff, 1, 0, 16 }, - Package() { 0x0000ffff, 2, 0, 17 }, - Package() { 0x0000ffff, 3, 0, 18 } }) - Name (IQDP, Package() { - Package() { 0x0000ffff, 0, _SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x0000ffff, 1, _SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0000ffff, 2, _SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0000ffff, 3, _SB.PCI0.LPCB.LNKC, 0 } }) - - Switch (ToInteger (Arg0)) { - /* PCIe Root Port 1 and 5 */ - Case (Package() { 1, 5 }) { - If (PICM) { - Return (IQAA) - } Else { - Return (IQAP) - } - } - - /* PCIe Root Port 2 and 6 */ - Case (Package() { 2, 6 }) { - If (PICM) { - Return (IQBA) - } Else { - Return (IQBP) - } - } - - /* PCIe Root Port 3 and 7 */ - Case (Package() { 3, 7 }) { - If (PICM) { - Return (IQCA) - } Else { - Return (IQCP) - } - } - - /* PCIe Root Port 4 and 8 */ - Case (Package() { 4, 8 }) { - If (PICM) { - Return (IQDA) - } Else { - Return (IQDP) - } - } - - Default { - If (PICM) { - Return (IQDA) - } Else { - Return (IQDP) - } - } - } -} - -Device (RP01) -{ - Name (_ADR, 0x001c0000) - - #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP02) -{ - Name (_ADR, 0x001c0001) - - #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP03) -{ - Name (_ADR, 0x001c0002) - - #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP04) -{ - Name (_ADR, 0x001c0003) - - #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP05) -{ - Name (_ADR, 0x001c0004) - - #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP06) -{ - Name (_ADR, 0x001c0005) - - #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP07) -{ - Name (_ADR, 0x001c0006) - - #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP08) -{ - Name (_ADR, 0x001c0007) - - #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} diff --git a/src/soc/intel/broadwell/pch/acpi/pcie_port.asl b/src/soc/intel/broadwell/pch/acpi/pcie_port.asl deleted file mode 100644 index 988c817..0000000 --- a/src/soc/intel/broadwell/pch/acpi/pcie_port.asl +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* Included in each PCIe Root Port device */ - -OperationRegion (RPCS, PCI_Config, 0x00, 0xFF) -Field (RPCS, AnyAcc, NoLock, Preserve) -{ - Offset (0x4c), // Link Capabilities - , 24, - RPPN, 8, // Root Port Number - Offset (0x5A), - , 3, - PDC, 1, - Offset (0xDF), - , 6, - HPCS, 1, -}
-
Angel Pons (Code Review) -
Michael Niewöhner (Code Review)