[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock

[Subrata Banik (Code Review)]

Attention is currently required from: Ashish Kumar Mishra, Dinesh Gehlot, Elyes Haouas, Eran Mitrani, Felix Singer, Jakub Czapiga, Jérémy Compostella, Kapil Porwal, Saurabh Mishra, Tarun.

Subrata Banik has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83354?usp=email )

Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
......................................................................

Patch Set 36:

(11 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/83354/comment/b0266911_44897cb9?usp... :
PS36, Line 16: 
Did you missed to highlighted that this CL also includes minimal code requires to compile the PTL SoC and mainbaord?

https://review.coreboot.org/c/coreboot/+/83354/comment/9c9b4ea2_b4ee9336?usp... :
PS36, Line 18: PSS
specify the acronyms

https://review.coreboot.org/c/coreboot/+/83354/comment/6af3c821_bcc1a6c8?usp... :
PS36, Line 18: v
V?

File src/soc/intel/pantherlake/Kconfig:

https://review.coreboot.org/c/coreboot/+/83354/comment/0c5d196a_fd76a870?usp... :
PS36, Line 53: 22
I guess we need to revisit this. 22 is too high for PTL-UH SKUs

https://review.coreboot.org/c/coreboot/+/83354/comment/590e478b_2f90585b?usp... :
PS36, Line 133: 10
as per Intel doc (731941), i read as `6 ports USB 2.0`

File src/soc/intel/pantherlake/bootblock/pcd.c:

https://review.coreboot.org/c/coreboot/+/83354/comment/16dc7c01_b561ae6b?usp... :
PS36, Line 129: 	if (pmc_reg_value != 0xffffffff) {
thoughts ?

```
    if (pmc_reg_value == 0xffffffff) {
       // show the warning msg as console is already initialised. This will help us incase  PCR_PSF8_TO_SHDW_PMC_REG_BASE is not proper or mistake in programming.
       return;
    }
```

File src/soc/intel/pantherlake/bootblock/report_platform.c:

https://review.coreboot.org/c/coreboot/+/83354/comment/6601d468_8073d50c?usp... :
PS36, Line 39: 	{ PCI_DID_INTEL_PTL_U_H_ESPI_0, "Pantherlake SOC-U" },
             : 	{ PCI_DID_INTEL_PTL_U_H_ESPI_1, "Pantherlake SOC-U SuperSKU" },
             : 	{ PCI_DID_INTEL_PTL_U_H_ESPI_2, "Pantherlake SOC-U Premium" },
             : 	{ PCI_DID_INTEL_PTL_U_H_ESPI_3, "Pantherlake SOC-U Base" },
             : 	{ PCI_DID_INTEL_PTL_U_H_ESPI_4, "Pantherlake SOC-U" },
             : 	{ PCI_DID_INTEL_PTL_U_H_ESPI_5, "Pantherlake SOC-U" },
             : 	{ PCI_DID_INTEL_PTL_U_H_ESPI_6, "Pantherlake SOC-U" },
             : 	{ PCI_DID_INTEL_PTL_U_H_ESPI_7, "Pantherlake SOC-U" },
             : 	{ PCI_DID_INTEL_PTL_U_H_ESPI_8, "Pantherlake SOC-U" },
             : 	{ PCI_DID_INTEL_PTL_U_H_ESPI_9, "Pantherlake SOC-U" },
             : 	{ PCI_DID_INTEL_PTL_U_H_ESPI_10, "Pantherlake SOC-U" },
             : 	{ PCI_DID_INTEL_PTL_U_H_ESPI_11, "Pantherlake SOC-U" },
             : 	{ PCI_DID_INTEL_PTL_U_H_ESPI_12, "Pantherlake SOC-U" },
             : 	{ PCI_DID_INTEL_PTL_U_H_ESPI_13, "Pantherlake SOC-U" },
             : 	{ PCI_DID_INTEL_PTL_U_H_ESPI_14, "Pantherlake SOC-U" },
             : 	{ PCI_DID_INTEL_PTL_U_H_ESPI_15, "Pantherlake SOC-U" },
             : 	{ PCI_DID_INTEL_PTL_U_H_ESPI_16, "Pantherlake SOC-U" },
             : 	{ PCI_DID_INTEL_PTL_U_H_ESPI_17, "Pantherlake SOC-U" },
             : 	{ PCI_DID_INTEL_PTL_U_H_ESPI_18, "Pantherlake SOC-U" },
             : 	{ PCI_DID_INTEL_PTL_U_H_ESPI_19, "Pantherlake SOC-U" },
             : 	{ PCI_DID_INTEL_PTL_U_H_ESPI_20, "Pantherlake SOC-U" },
             : 	{ PCI_DID_INTEL_PTL_U_H_ESPI_21, "Pantherlake SOC-U" },
             : 	{ PCI_DID_INTEL_PTL_U_H_ESPI_22, "Pantherlake SOC-U" },
             : 	{ PCI_DID_INTEL_PTL_U_H_ESPI_23, "Pantherlake SOC-U" },
             : 	{ PCI_DID_INTEL_PTL_U_H_ESPI_24, "Pantherlake SOC-U" },
             : 	{ PCI_DID_INTEL_PTL_U_H_ESPI_25, "Pantherlake SOC-U" },
             : 	{ PCI_DID_INTEL_PTL_U_H_ESPI_26, "Pantherlake SOC-U" },
             : 	{ PCI_DID_INTEL_PTL_U_H_ESPI_27, "Pantherlake SOC-U" },
             : 	{ PCI_DID_INTEL_PTL_U_H_ESPI_28, "Pantherlake SOC-U" },
             : 	{ PCI_DID_INTEL_PTL_U_H_ESPI_29, "Pantherlake SOC-U" },
             : 	{ PCI_DID_INTEL_PTL_U_H_ESPI_30, "Pantherlake SOC-U" },
             : 	{ PCI_DID_INTEL_PTL_U_H_ESPI_31, "Pantherlake SOC-U" },
should be specify these as "Panther Lake SoC-UH"

https://review.coreboot.org/c/coreboot/+/83354/comment/c4102a9c_d0ca17d2?usp... :
PS36, Line 109: GT2
name and macro description are not matching

https://review.coreboot.org/c/coreboot/+/83354/comment/d6a0df25_eca656e7?usp... :
PS36, Line 110: GT2
same

https://review.coreboot.org/c/coreboot/+/83354/comment/8ccdbca9_109073d2?usp... :
PS36, Line 114: static inline uint8_t get_dev_revision(pci_devfn_t dev)
              : {
              : 	return pci_read_config8(dev, PCI_REVISION_ID);
              : }
              : 
              : static inline uint16_t get_dev_id(pci_devfn_t dev)
              : {
              : 	return pci_read_config16(dev, PCI_DEVICE_ID);
              : }
              : 
may be good topic for common code

File src/soc/intel/pantherlake/include/soc/soc_info.h:

https://review.coreboot.org/c/coreboot/+/83354/comment/e960d333_2d20709e?usp... :
PS36, Line 6: uint8_t get_soctype(void);
why we still have this ?