Attention is currently required from: Angel Pons, Felix Singer, Maxim, Michał Kopeć, Michał Żygowski, Nicholas Chin, Paul Menzel.
Alicja Michalska has posted comments on this change by Alicja Michalska. ( https://review.coreboot.org/c/coreboot/+/80853?usp=email )
Change subject: mb/erying: Add Erying Polestar G613 Pro (TGL-H) ......................................................................
Patch Set 11:
(30 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80853/comment/0f783630_8a12f2ad?usp... : PS8, Line 39: Likewise, I can't wrap my head around PCI-E AERs I'm getting if I boot : the machine without `pcie_aspm=off` parameter: : - BadTLP : - BadDLLP : - Timeout : - Rollover
RP5, PEG0, PEG1. Yes, it's enabled in stock firmware: […]
Done
File src/mainboard/erying/tgl/Kconfig:
https://review.coreboot.org/c/coreboot/+/80853/comment/29597625_c6aea2ef?usp... : PS8, Line 29: config PCIEXP_ASPM : default n : : config PCIEXP_CLK_PM : default n : : config PCIEXP_L1_SUB_STATE : default n
It does enable/disable ASPM based on Kconfig setting. […]
I've set values to "0" in ramstage which would have the same result, but added this as preventive measure. It does make a difference, new patch series fixes PCI-E instability.
https://review.coreboot.org/c/coreboot/+/80853/comment/630f143b_b6e78bd7?usp... : PS8, Line 39: default y
Why?
Done
File src/mainboard/erying/tgl/Kconfig.name:
https://review.coreboot.org/c/coreboot/+/80853/comment/5b53157d_9c944adb?usp... : PS8, Line 4: bool "erying-tgl"
There are no mITX versions of TGL platform, so it would be safe to leave it as-it. […]
Done
File src/mainboard/erying/tgl/gpio.h:
https://review.coreboot.org/c/coreboot/+/80853/comment/4c7ab693_266fd588?usp... : PS8, Line 168: PAD_CFG_NF(GPD9, NONE, PWROK, NF1), /* SLP_WLAN# */
`please, no space before tabs` […]
Done
File src/mainboard/erying/tgl/ramstage.c:
https://review.coreboot.org/c/coreboot/+/80853/comment/3b9a89d1_d1b434f6?usp... : PS8, Line 21: params->CpuPcieRpAdvancedErrorReporting[0] = 1;
Sure, but then AERs will still happen - we simply won't know about it.
Done
https://review.coreboot.org/c/coreboot/+/80853/comment/7a476f2e_4054bd99?usp... : PS8, Line 24: params->CpuPcieRpPtmEnabled[0] = 1;
Why?
Done
https://review.coreboot.org/c/coreboot/+/80853/comment/8fc7ee6e_118efb7e?usp... : PS8, Line 45: params->PcieRpPmSci[4] = 1;
Why?
Done
https://review.coreboot.org/c/coreboot/+/80853/comment/d40fcfb0_2f1cea0a?usp... : PS8, Line 71: params->ITbtPcieTunnelingForUsb4 = 0;
Now that I think about it, probably no. […]
Done
https://review.coreboot.org/c/coreboot/+/80853/comment/2fecd8a3_1f53637f?usp... : PS8, Line 72: params->PchUsbOverCurrentEnable = 0;
It was left there for debugging and I forgot about it. […]
Done
File src/mainboard/erying/tgl/romstage_fsp_params.c:
https://review.coreboot.org/c/coreboot/+/80853/comment/e6f2340c_0cd37ffd?usp... : PS8, Line 24: mupd->FspmConfig.EnableAbove4GBMmio = 1;
Shouldn't this be configurable?
Technically yes, but I don't see a Kconfig option for it in coreboot (maybe I'm just missing something).
https://review.coreboot.org/c/coreboot/+/80853/comment/ce6aaa6a_7dea3bee?usp... : PS8, Line 25: mupd->FspmConfig.OcSupport = 1; : mupd->FspmConfig.OcLock = 0;
Should be turned into a config option at SoC level.
Likewise, though I will check if it's necessary in the first place.
https://review.coreboot.org/c/coreboot/+/80853/comment/2c9e0652_25447ed5?usp... : PS8, Line 28: // iGPU : mupd->FspmConfig.GttSize = 3; // 8MB : mupd->FspmConfig.ApertureSize = 3; // 512MB : mupd->FspmConfig.GtPsmiSupport = 0; : mupd->FspmConfig.IgdDvmt50PreAlloc = 2; // 64MB
Should be configurable, if set at all. […]
Yes, without configuring those options, iGPU would crash spectacularly with framebuffer corruption or GPU reset.
https://review.coreboot.org/c/coreboot/+/80853/comment/307758c8_454eaf82?usp... : PS8, Line 35: mupd->FspmConfig.CpuPcieRpPcieSpeed[0] = 0; // Auto : mupd->FspmConfig.CpuPcieRpPcieSpeed[1] = 0; // Auto
There should be no need to set these.
Acknowledged
https://review.coreboot.org/c/coreboot/+/80853/comment/76eab68d_5d641a46?usp... : PS8, Line 37: mupd->FspmConfig.CpuPcieRpCdrRelock[0] = 1; : mupd->FspmConfig.CpuPcieRpCdrRelock[1] = 1;
Why?
Acknowledged
https://review.coreboot.org/c/coreboot/+/80853/comment/277bfe33_72d94131?usp... : PS8, Line 39: mupd->FspmConfig.CpuPcieNewFom[0] = 1; : mupd->FspmConfig.CpuPcieNewFom[1] = 1;
Why? I don't know what exactly this does, but the default is 0. […]
Acknowledged
https://review.coreboot.org/c/coreboot/+/80853/comment/9b1f3986_2fe868fd?usp... : PS8, Line 43: mupd->FspmConfig.DmiMaxLinkSpeed = 3;
No need
Without setting this parameter, DMI behaves... erratically, slowly dropping link speed
https://review.coreboot.org/c/coreboot/+/80853/comment/ce2e6ca9_a2edf79e?usp... : PS8, Line 44: mupd->FspmConfig.DmiAspm = 0; : mupd->FspmConfig.DmiAspmCtrl = 0;
DMI ASPM is independent from PCIe ASPM. Please remove.
Yes, I've set this on purpose. System is so unstable without this option being set that it doesn't make it to loading the kernel from NVMe drive.
It's necessary, so leaving as-is.
https://review.coreboot.org/c/coreboot/+/80853/comment/15c4fed4_d474f72d?usp... : PS8, Line 48: mupd->FspmConfig.SpdProfileSelected = 0; // Default profile
Any reason to set this?
Like with RefClk, I'm leaving an option for users to easily enable XMP.
Tested, working and stable (seemingly first DDR4 mainboard in coreboot tree with working XMP). I'm planning to move from SMMSTORE to CMOS in the future and configure it based on CMOS value, which users will be able to configure by setting it in UiApp in EDK2 or some other mean.
https://review.coreboot.org/c/coreboot/+/80853/comment/251413da_33a4eea5?usp... : PS8, Line 49: mupd->FspmConfig.RefClk = 0; // 133MHz
Any reason to set this?
Not sure which one FSP picks as default, RefClk 100MHz is less stable than 133MHz (for whatever reason).
https://review.coreboot.org/c/coreboot/+/80853/comment/e0fe3c74_1ae9071a?usp... : PS8, Line 50: mupd->FspmConfig.VddVoltage = 1350; // 1.35V (Applicable only with XMP Profile 1)
Does your board have the means to change the DIMM voltage? If not, this is just lying to MRC.
Yes, based on XMP profile.
https://review.coreboot.org/c/coreboot/+/80853/comment/6d3664ac_8ac33267?usp... : PS8, Line 51: mupd->FspmConfig.Ratio = 0; // Auto : mupd->FspmConfig.RingDownBin = 0; : mupd->FspmConfig.GearRatio = 0; // Auto
Aren't these the defaults?
Changed those in recent patch.
https://review.coreboot.org/c/coreboot/+/80853/comment/6b209f7b_34ef18bf?usp... : PS8, Line 54: mupd->FspmConfig.ECT = 1;
Early Command Training is usually disabled for DDR4, any reason to enable it here?
AFAIK necessary for XMP to work?
https://review.coreboot.org/c/coreboot/+/80853/comment/498b195c_2627541f?usp... : PS8, Line 64: mupd->FspmConfig.WRVC1D = 1; : mupd->FspmConfig.WRVC1D = 1;
This is set twice, shouldn't be set at all anyway.
Keen eye, thanks!
https://review.coreboot.org/c/coreboot/+/80853/comment/7e294765_76236ee3?usp... : PS8, Line 54: mupd->FspmConfig.ECT = 1; : mupd->FspmConfig.LCT = 1; : mupd->FspmConfig.SOT = 1; : mupd->FspmConfig.ERDMPRTC2D = 0; : mupd->FspmConfig.RDMPRT = 1; : mupd->FspmConfig.RCVET = 1; : mupd->FspmConfig.JWRL = 1; : mupd->FspmConfig.EWRTC2D = 1; : mupd->FspmConfig.ERDTC2D = 1; : mupd->FspmConfig.WRTC2D = 1; : mupd->FspmConfig.WRVC1D = 1; : mupd->FspmConfig.WRVC1D = 1; : mupd->FspmConfig.DIMMODTT = 1; : mupd->FspmConfig.DIMMRONT = 1; : mupd->FspmConfig.WRDSEQT = 1; : mupd->FspmConfig.WRSRT = 0; : mupd->FspmConfig.RDODTT = 1; : mupd->FspmConfig.RDEQT = 1; : mupd->FspmConfig.RDAPT = 1; : mupd->FspmConfig.RDTC2D = 1; : mupd->FspmConfig.WRVC2D = 1; : mupd->FspmConfig.RDVC2D = 1; : mupd->FspmConfig.CMDVC = 1; : mupd->FspmConfig.MrcSafeConfig = 0; : mupd->FspmConfig.LpDdrDqDqsReTraining = 1; : mupd->FspmConfig.SafeMode = 0; : mupd->FspmConfig.OverrideDowngradeForMixedMemory = 0; : mupd->FspmConfig.MemTestOnWarmBoot = 1;
Why change this? Changing which MRC training steps get executed is very risky as it can increase the […]
Acknowledged
https://review.coreboot.org/c/coreboot/+/80853/comment/b62c059e_aa8be891?usp... : PS8, Line 82: mupd->FspmConfig.DdrFreqLimit = 2933; // Setting to auto for now.
That doesn't look like "auto"
Yes, that was a mistake on my part. I've been blaming my code for unstable memory, while in reality... my RAM became faulty.
Both D0 and D1 work perfectly with 3200MHz XMP enabled now, changed in recent patch.
https://review.coreboot.org/c/coreboot/+/80853/comment/02568ea1_edf93c72?usp... : PS8, Line 83: mupd->FspmConfig.SaGv = 0;
Does it matter for TGL-H?
Likely not
https://review.coreboot.org/c/coreboot/+/80853/comment/b989c247_08007ebc?usp... : PS8, Line 85: mupd->FspmConfig.NModeSupport = 1; // Board type is 1N (1DPC).
N-Mode (command rate) is not bound to DPC (the number of DIMMs per channel). […]
I see, thank you.
https://review.coreboot.org/c/coreboot/+/80853/comment/bebfb275_8993828a?usp... : PS8, Line 86: mupd->FspmConfig.RhPrevention = 0;
Please don't force disable Row Hammer prevention upon others. […]
Acknowledged
https://review.coreboot.org/c/coreboot/+/80853/comment/56063848_ec367ff0?usp... : PS8, Line 87: mupd->FspmConfig.RefreshWm = 1; : mupd->FspmConfig.ExitOnFailure = 1;
Why set these?
Copied from vendor's firmware for debugging purposes, I suppose it's safe to remove them.
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Alicja Michalska (Code Review)