Attention is currently required from: Felix Singer, Nico Huber, Tim Wawrzynczak, Angel Pons, Arthur Heymans, Nick Vaccaro, Andrey Petrov, Patrick Rudolph. Hello Felix Singer, build bot (Jenkins), Tim Wawrzynczak, Angel Pons, Arthur Heymans, Nick Vaccaro, Tim Wawrzynczak, Andrey Petrov, Patrick Rudolph, EricR Lai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/60441
to look at the new patch set (#3).
Change subject: soc/intel/alderlake: Add option to make MRC log silent ......................................................................
soc/intel/alderlake: Add option to make MRC log silent
Typically, FSP-M aka MRC debug log level is default set to `3` meaning prints all `Load, Error, Warnings & Info` Messages.
Sometimes it's too much information to parse even when users aren't required to have such detailed information hence, implemented `fsp_map_console_log_level()` that maps coreboot console log level to FSP-M debug log level and suppress verbose MRC debug messages unless `HAVE_DEBUG_RAM_SETUP` config is enabled.
TEST=FSP-M debug log suggested default `SerialDebugMrcLevel` UPD value is `2`. While the user selects `HAVE_DEBUG_RAM_SETUP` config `SerialDebugMrcLevel` UPD value is overridden to '5' aka verbose.
Signed-off-by: Subrata Banik subratabanik@google.com Change-Id: Iea3b32feca0893a83fdf700798b0883d26ccc718 --- M src/soc/intel/alderlake/romstage/fsp_params.c 1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/60441/3