Change in ...coreboot[master]: nb/intel/i945: Use DEBUG_RAM_SETUP - coreboot-gerrit

24 Mar 2019

Kyösti Mälkki has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32032 )
Change subject: nb/intel/i945: Use DEBUG_RAM_SETUP
......................................................................
nb/intel/i945: Use DEBUG_RAM_SETUP
Avoid preprocessor here, also we never set loglevel
to value of >8 so the call would not be made.
The calls to ram_check() were removed, for a long
time that function has not tested start..stop region.
Change-Id: Ib952b8905c29a5c5c289027071eb6ff59aaa330b
Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32032
Tested-by: build bot (Jenkins) no-reply@coreboot.org
Reviewed-by: HAOUAS Elyes ehaouas@noos.fr
Reviewed-by: Angel Pons th3fanbus@gmail.com
Reviewed-by: Arthur Heymans arthur@aheymans.xyz
---
M src/mainboard/asus/p5gc-mx/romstage.c
M src/mainboard/getac/p470/romstage.c
M src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c
M src/mainboard/ibase/mb899/romstage.c
M src/mainboard/intel/d945gclf/romstage.c
M src/mainboard/kontron/986lcd-m/romstage.c
M src/mainboard/lenovo/t60/romstage.c
M src/mainboard/lenovo/x60/romstage.c
M src/mainboard/lenovo/z61t/romstage.c
M src/mainboard/roda/rk886ex/romstage.c
M src/northbridge/intel/i945/early_init.c
M src/northbridge/intel/i945/i945.h
M src/northbridge/intel/i945/raminit.c
M src/northbridge/intel/i945/raminit.h
14 files changed, 23 insertions(+), 52 deletions(-)
Approvals:
  build bot (Jenkins): Verified
  HAOUAS Elyes: Looks good to me, but someone else must approve
  Arthur Heymans: Looks good to me, approved
  Angel Pons: Looks good to me, but someone else must approve

diff --git a/src/mainboard/asus/p5gc-mx/romstage.c b/src/mainboard/asus/p5gc-mx/romstage.c
index ffb3bf9..a93009f 100644
--- a/src/mainboard/asus/p5gc-mx/romstage.c
+++ b/src/mainboard/asus/p5gc-mx/romstage.c
@@ -220,9 +220,8 @@
    /* Enable SPD ROMs and DDR-II DRAM */
    enable_smbus();
-#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
-	dump_spd_registers();
-#endif
+	if (CONFIG(DEBUG_RAM_SETUP))
+		dump_spd_registers();
sdram_initialize(s3resume ? 2 : boot_mode, NULL);
diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c
index 423b4e8..461e394 100644
--- a/src/mainboard/getac/p470/romstage.c
+++ b/src/mainboard/getac/p470/romstage.c
@@ -271,9 +271,8 @@
    /* Enable SPD ROMs and DDR-II DRAM */
    enable_smbus();
-#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
-	dump_spd_registers();
-#endif
+	if (CONFIG(DEBUG_RAM_SETUP))
+		dump_spd_registers();
sdram_initialize(s3resume ? 2 : 0, NULL);
diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c
index b2d4bb4..d23df35 100644
--- a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c
+++ b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c
@@ -172,9 +172,8 @@
    /* Enable SPD ROMs and DDR-II DRAM */
    enable_smbus();
-#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
-	dump_spd_registers();
-#endif
+	if (CONFIG(DEBUG_RAM_SETUP))
+		dump_spd_registers();
sdram_initialize(s3resume ? 2 : boot_mode, NULL);
diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c
index 1257fa5..49bb1e5 100644
--- a/src/mainboard/ibase/mb899/romstage.c
+++ b/src/mainboard/ibase/mb899/romstage.c
@@ -231,9 +231,8 @@
    /* Enable SPD ROMs and DDR-II DRAM */
    enable_smbus();
-#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
-	dump_spd_registers();
-#endif
+	if (CONFIG(DEBUG_RAM_SETUP))
+		dump_spd_registers();
sdram_initialize(s3resume ? 2 : 0, NULL);
diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c
index 18a7721..6cb24a6 100644
--- a/src/mainboard/intel/d945gclf/romstage.c
+++ b/src/mainboard/intel/d945gclf/romstage.c
@@ -151,9 +151,8 @@
    /* Enable SPD ROMs and DDR-II DRAM */
    enable_smbus();
-#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
-	dump_spd_registers();
-#endif
+	if (CONFIG(DEBUG_RAM_SETUP))
+		dump_spd_registers();
sdram_initialize(s3resume ? 2 : boot_mode, NULL);
diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c
index 52432a0..394522c 100644
--- a/src/mainboard/kontron/986lcd-m/romstage.c
+++ b/src/mainboard/kontron/986lcd-m/romstage.c
@@ -279,9 +279,8 @@
    /* Enable SPD ROMs and DDR-II DRAM */
    enable_smbus();
-#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
-	dump_spd_registers();
-#endif
+	if (CONFIG(DEBUG_RAM_SETUP))
+		dump_spd_registers();
sdram_initialize(s3resume ? 2 : 0, NULL);
diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c
index 070ee59..0ca690b 100644
--- a/src/mainboard/lenovo/t60/romstage.c
+++ b/src/mainboard/lenovo/t60/romstage.c
@@ -208,9 +208,8 @@
    /* Enable SPD ROMs and DDR-II DRAM */
    enable_smbus();
-#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
-	dump_spd_registers();
-#endif
+	if (CONFIG(DEBUG_RAM_SETUP))
+		dump_spd_registers();
sdram_initialize(s3resume ? 2 : 0, spd_addrmap);
diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c
index 39e0ed5..e655ddf 100644
--- a/src/mainboard/lenovo/x60/romstage.c
+++ b/src/mainboard/lenovo/x60/romstage.c
@@ -211,9 +211,8 @@
    /* Enable SPD ROMs and DDR-II DRAM */
    enable_smbus();
-#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
-	dump_spd_registers();
-#endif
+	if (CONFIG(DEBUG_RAM_SETUP))
+		dump_spd_registers();
sdram_initialize(s3resume ? 2 : 0, spd_addrmap);
diff --git a/src/mainboard/lenovo/z61t/romstage.c b/src/mainboard/lenovo/z61t/romstage.c
index 45cd9ec..0c1d7b9 100644
--- a/src/mainboard/lenovo/z61t/romstage.c
+++ b/src/mainboard/lenovo/z61t/romstage.c
@@ -209,9 +209,8 @@
    /* Enable SPD ROMs and DDR-II DRAM */
    enable_smbus();
-#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
-	dump_spd_registers();
-#endif
+	if (CONFIG(DEBUG_RAM_SETUP))
+		dump_spd_registers();
sdram_initialize(s3resume ? 2 : 0, spd_addrmap);
diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c
index dbc4b6c..46ef808 100644
--- a/src/mainboard/roda/rk886ex/romstage.c
+++ b/src/mainboard/roda/rk886ex/romstage.c
@@ -244,9 +244,8 @@
    /* Enable SPD ROMs and DDR-II DRAM */
    enable_smbus();
-#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
-	dump_spd_registers();
-#endif
+	if (CONFIG(DEBUG_RAM_SETUP))
+		dump_spd_registers();
sdram_initialize(s3resume ? 2 : 0, NULL);
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index d3ed277..08dd675 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -940,22 +940,8 @@
i945_setup_root_complex_topology();
-#if !CONFIG(HAVE_ACPI_RESUME)
-#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
-#if CONFIG(DEBUG_RAM_SETUP)
-	sdram_dump_mchbar_registers();
-
-	{
-		/* This will not work if TSEG is in place! */
-		u32 tom = pci_read_config32(PCI_DEV(0, 2, 0), BSM);
-
-		printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom);
-		ram_check(0x00000000, 0x000a0000);
-		ram_check(0x00100000, tom);
-	}
-#endif
-#endif
-#endif
+	if (CONFIG(DEBUG_RAM_SETUP))
+		sdram_dump_mchbar_registers();
MCHBAR16(SSKPD) = 0xCAFE;
diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h
index 8c08241..ebcc8bc 100644
--- a/src/northbridge/intel/i945/i945.h
+++ b/src/northbridge/intel/i945/i945.h
@@ -375,6 +375,7 @@
 void dump_pci_device(unsigned int dev);
 void dump_pci_devices(void);
 void dump_spd_registers(void);
+void sdram_dump_mchbar_registers(void);
u32 decode_igd_memory_size(u32 gms);
 u32 decode_tseg_size(const u8 esmramc);
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index a93cf1e..05b5777 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -96,7 +96,6 @@
    read32((void *)offset);
 }
-#if CONFIG(DEBUG_RAM_SETUP)
 void sdram_dump_mchbar_registers(void)
 {
    int i;
@@ -108,7 +107,6 @@
    	printk(BIOS_DEBUG, "0x%04x: 0x%08x\n", i, MCHBAR32(i));
    }
 }
-#endif
static int memclk(void)
 {
diff --git a/src/northbridge/intel/i945/raminit.h b/src/northbridge/intel/i945/raminit.h
index 2d1eee6..e9e66d1 100644
--- a/src/northbridge/intel/i945/raminit.h
+++ b/src/northbridge/intel/i945/raminit.h
@@ -69,8 +69,4 @@
 void sdram_initialize(int boot_path, const u8 *sdram_addresses);
 int fixup_i945_errata(void);
 void udelay(u32 us);
-
-#if CONFIG(DEBUG_RAM_SETUP)
-void sdram_dump_mchbar_registers(void);
-#endif
 #endif				/* RAMINIT_H */
-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ib952b8905c29a5c5c289027071eb6ff59aaa330b
Gerrit-Change-Number: 32032
Gerrit-PatchSet: 2
Gerrit-Owner: Kyösti Mälkki kyosti.malkki@gmail.com
Gerrit-Reviewer: Alexander Couzens lynxis@fe80.eu
Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com
Gerrit-Reviewer: Arthur Heymans arthur@aheymans.xyz
Gerrit-Reviewer: HAOUAS Elyes ehaouas@noos.fr
Gerrit-Reviewer: Kyösti Mälkki kyosti.malkki@gmail.com
Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org
Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org
Gerrit-MessageType: merged



    