Hello Matt DeVillier,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/35923
to review the following change.
Change subject: mb/intel/saddlebrook: migrate to FSP 2.0 ......................................................................
mb/intel/saddlebrook: migrate to FSP 2.0
This patch is part of the patch series to drop support for FSP 1.1 in soc/intel/skylake.
The following modifications have been done to migrate the board(s) from FSP 1.1 to FSP 2.0:
- remove deprecated devicetree VR_RING domain (only 4 domains in FSP 2.0) - add AC/DC loadline values to devicetree (see TODO) - add FSP parameter DmiVc1 (see TODO) - set FSP board type to "mobile"
TODO: - check loadline values again - loadline values in devicetree maybe can dropped again, as Maxim is working on adding missing loadline values in CB:35167 - find out why some boards set DmiVc1 - testing
Change-Id: I7481f3413de6780df01d9b769bd4f16d439f087c Signed-off-by: Michael Niewöhner foss@mniewoehner.de Signed-off-by: Matt DeVillier matt.devillier@gmail.com --- M src/mainboard/intel/saddlebrook/Kconfig M src/mainboard/intel/saddlebrook/devicetree.cb M src/mainboard/intel/saddlebrook/ramstage.c M src/mainboard/intel/saddlebrook/romstage.c 4 files changed, 73 insertions(+), 70 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35923/1
diff --git a/src/mainboard/intel/saddlebrook/Kconfig b/src/mainboard/intel/saddlebrook/Kconfig index 934c15a..3fb694a 100644 --- a/src/mainboard/intel/saddlebrook/Kconfig +++ b/src/mainboard/intel/saddlebrook/Kconfig @@ -32,6 +32,7 @@ select HAVE_CMOS_DEFAULT select MAINBOARD_USES_IFD_GBE_REGION select USE_INTEL_FSP_MP_INIT + select MAINBOARD_USES_FSP2_0
config IRQ_SLOT_COUNT int diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index 3322bf8..1d9a71b 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -61,82 +61,80 @@
register "serirq_mode" = "SERIRQ_CONTINUOUS"
- # VR Settings Configuration for 5 Domains - #+----------------+-------+-------+-------------+-------------+-------+ - #| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT | - #+----------------+-------+-------+-------------+-------------+-------+ - #| Psi1Threshold | 20A | 20A | 20A | 20A | 20A | - #| Psi2Threshold | 4A | 5A | 5A | 5A | 5A | - #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A | - #| Psi3Enable | 1 | 1 | 1 | 1 | 1 | - #| Psi4Enable | 1 | 1 | 1 | 1 | 1 | - #| ImonSlope | 0 | 0 | 0 | 0 | 0 | - #| ImonOffset | 0 | 0 | 0 | 0 | 0 | - #| IccMax | 7A | 34A | 34A | 35A | 35A | - #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V | - #+----------------+-------+-------+-------------+-------------+-------+ + # VR Settings Configuration for 4 Domains + #+----------------+-----------+-----------+-------------+----------+ + #| Domain/Setting | SA | IA | GT Unsliced | GT | + #+----------------+-----------+-----------+-------------+----------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 4A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| IccMax | 7A | 34A | 35A | 35A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #| AC LoadLine | 15 mOhm | 5.7 mOhm | 5.2 mOhm | 5.2 mOhm | + #| DC LoadLine | 14.3 mOhm | 4.83 mOhm | 4.2 mOhm | 4.2 mOhm | + #+----------------+-----------+-----------+-------------+----------+ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ - .vr_config_enable = 1, \ - .psi1threshold = 0x50, \ - .psi2threshold = 0x10, \ - .psi3threshold = 0x4, \ - .psi3enable = 1, \ - .psi4enable = 1, \ - .imon_slope = 0x0, \ - .imon_offset = 0x0, \ - .icc_max = 0x1C, \ - .voltage_limit = 0x5F0 \ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(4), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(7), + .voltage_limit = 1520, + .ac_loadline = 1500, + .dc_loadline = 1430, }"
register "domain_vr_config[VR_IA_CORE]" = "{ - .vr_config_enable = 1, \ - .psi1threshold = 0x50, \ - .psi2threshold = 0x14, \ - .psi3threshold = 0x4, \ - .psi3enable = 1, \ - .psi4enable = 1, \ - .imon_slope = 0x0, \ - .imon_offset = 0x0, \ - .icc_max = 0x88, \ - .voltage_limit = 0x5F0 \ - }" - register "domain_vr_config[VR_RING]" = "{ - .vr_config_enable = 1, \ - .psi1threshold = 0x50, \ - .psi2threshold = 0x14, \ - .psi3threshold = 0x4, \ - .psi3enable = 1, \ - .psi4enable = 1, \ - .imon_slope = 0x0, \ - .imon_offset = 0x0, \ - .icc_max = 0x88, \ - .voltage_limit = 0x5F0, \ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(34), + .voltage_limit = 1520, + .ac_loadline = 570, + .dc_loadline = 483, }"
register "domain_vr_config[VR_GT_UNSLICED]" = "{ - .vr_config_enable = 1, \ - .psi1threshold = 0x50, \ - .psi2threshold = 0x14, \ - .psi3threshold = 0x4, \ - .psi3enable = 1, \ - .psi4enable = 1, \ - .imon_slope = 0x0, \ - .imon_offset = 0x0, \ - .icc_max = 0x8C ,\ - .voltage_limit = 0x5F0 \ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(35), + .voltage_limit = 1520, + .ac_loadline = 520, + .dc_loadline = 420, }"
register "domain_vr_config[VR_GT_SLICED]" = "{ - .vr_config_enable = 1, \ - .psi1threshold = 0x50, \ - .psi2threshold = 0x14, \ - .psi3threshold = 0x4, \ - .psi3enable = 1, \ - .psi4enable = 1, \ - .imon_slope = 0x0, \ - .imon_offset = 0x0, \ - .icc_max = 0x8C, \ - .voltage_limit = 0x5F0 \ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(35), + .voltage_limit = 1520, + .ac_loadline = 520, + .dc_loadline = 420, }"
# Enable x1 slot diff --git a/src/mainboard/intel/saddlebrook/ramstage.c b/src/mainboard/intel/saddlebrook/ramstage.c index 42477e6..ed37681 100644 --- a/src/mainboard/intel/saddlebrook/ramstage.c +++ b/src/mainboard/intel/saddlebrook/ramstage.c @@ -16,7 +16,7 @@ #include <soc/ramstage.h> #include "gpio.h"
-void mainboard_silicon_init_params(SILICON_INIT_UPD *params) +void mainboard_silicon_init_params(FSP_SIL_UPD *params) { /* Configure pads prior to SiliconInit() in case there's any * dependencies during hardware initialization. */ diff --git a/src/mainboard/intel/saddlebrook/romstage.c b/src/mainboard/intel/saddlebrook/romstage.c index 46c2cdd..aa218fd 100644 --- a/src/mainboard/intel/saddlebrook/romstage.c +++ b/src/mainboard/intel/saddlebrook/romstage.c @@ -25,10 +25,10 @@ #include <spd_bin.h>
-void mainboard_memory_init_params( - struct romstage_params *params, - MEMORY_INIT_UPD *memory_params) +void mainboard_memory_init_params(FSPM_UPD *mupd) { + FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; + struct spd_block blk = { .addr_map = { 0x50, 0x52, }, }; @@ -59,4 +59,8 @@ /* update spd length*/ memory_params->MemorySpdDataLen = blk.len; memory_params->DqPinsInterleaved = TRUE; + + mem_cfg->UserBd = BOARD_TYPE_MOBILE; + + mupd->FspmTestConfig.DmiVc1 = 1; }
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35923 )
Change subject: mb/intel/saddlebrook: migrate to FSP 2.0 ......................................................................
Uploaded patch set 2: Patch Set 1 was rebased.
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35923 )
Change subject: mb/intel/saddlebrook: migrate to FSP 2.0 ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35923/3/src/mainboard/intel/saddleb... File src/mainboard/intel/saddlebrook/romstage.c:
https://review.coreboot.org/c/coreboot/+/35923/3/src/mainboard/intel/saddleb... PS3, Line 40: memory_params- This breaking everything.
Matt DeVillier has uploaded a new patch set (#4) to the change originally created by Michael Niewöhner. ( https://review.coreboot.org/c/coreboot/+/35923 )
Change subject: mb/intel/saddlebrook: migrate to FSP 2.0 ......................................................................
mb/intel/saddlebrook: migrate to FSP 2.0
This patch is part of the patch series to drop support for FSP 1.1 in soc/intel/skylake.
The following modifications have been done to migrate the board(s) from FSP 1.1 to FSP 2.0:
- remove deprecated devicetree VR_RING domain (only 4 domains in FSP 2.0) - add AC/DC loadline values to devicetree (see TODO) - add FSP parameter DmiVc1 (see TODO) - set FSP board type to "mobile"
TODO: - check loadline values again - loadline values in devicetree maybe can dropped again, as Maxim is working on adding missing loadline values in CB:35167 - find out why some boards set DmiVc1 - testing
Change-Id: I7481f3413de6780df01d9b769bd4f16d439f087c Signed-off-by: Michael Niewöhner foss@mniewoehner.de Signed-off-by: Matt DeVillier matt.devillier@gmail.com --- M src/mainboard/intel/saddlebrook/Kconfig M src/mainboard/intel/saddlebrook/devicetree.cb M src/mainboard/intel/saddlebrook/ramstage.c M src/mainboard/intel/saddlebrook/romstage.c 4 files changed, 85 insertions(+), 82 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35923/4
Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35923 )
Change subject: mb/intel/saddlebrook: migrate to FSP 2.0 ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35923/3/src/mainboard/intel/saddleb... File src/mainboard/intel/saddlebrook/romstage.c:
https://review.coreboot.org/c/coreboot/+/35923/3/src/mainboard/intel/saddleb... PS3, Line 40: memory_params-
This breaking everything.
Done
Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35923 )
Change subject: mb/intel/saddlebrook: migrate to FSP 2.0 ......................................................................
Patch Set 5: Code-Review+2
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35923 )
Change subject: mb/intel/saddlebrook: migrate to FSP 2.0 ......................................................................
Uploaded patch set 7: Patch Set 6 was rebased.
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35923 )
Change subject: mb/intel/saddlebrook: migrate to FSP 2.0 ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35923/7//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35923/7//COMMIT_MSG@17 PS7, Line 17: TODO: : - testing what about testing?
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35923 )
Change subject: mb/intel/saddlebrook: migrate to FSP 2.0 ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35923/7//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35923/7//COMMIT_MSG@17 PS7, Line 17: TODO: : - testing
what about testing?
well, shouldn't this be tested before merging? I don't have the board, so someone else needs to test it
Michael Niewöhner has restored this change. ( https://review.coreboot.org/c/coreboot/+/35923 )
Change subject: mb/intel/saddlebrook: migrate to FSP 2.0 ......................................................................
Restored
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35923 )
Change subject: mb/intel/saddlebrook: migrate to FSP 2.0 ......................................................................
Patch Set 7:
@PraveenX would you mind testing this?
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35923 )
Change subject: mb/intel/saddlebrook: migrate to FSP 2.0 ......................................................................
Uploaded patch set 8: Patch Set 7 was rebased.
Wim Vervoorn has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35923 )
Change subject: mb/intel/saddlebrook: migrate to FSP 2.0 ......................................................................
Patch Set 8: Code-Review+1
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35923 )
Change subject: mb/intel/saddlebrook: migrate to FSP 2.0 ......................................................................
Uploaded patch set 9: Patch Set 8 was rebased.
PraveenX Hodagatta Pranesh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35923 )
Change subject: mb/intel/saddlebrook: migrate to FSP 2.0 ......................................................................
Patch Set 9:
Patch Set 7:
@PraveenX would you mind testing this?
what is the expectation for test ? Boot test ?
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35923 )
Change subject: mb/intel/saddlebrook: migrate to FSP 2.0 ......................................................................
Patch Set 9:
Patch Set 9:
Patch Set 7:
@PraveenX would you mind testing this?
what is the expectation for test ? Boot test ?
Well, in the best case the device boots and works just like before :-)
PraveenX Hodagatta Pranesh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35923 )
Change subject: mb/intel/saddlebrook: migrate to FSP 2.0 ......................................................................
Patch Set 9:
Patch Set 9:
Patch Set 9:
Patch Set 7:
@PraveenX would you mind testing this?
what is the expectation for test ? Boot test ?
Well, in the best case the device boots and works just like before :-)
Able to build with this patch,initially not able to boot & cannot see serial logs. later changing to 16MB ROM SIZE(adding decriptor.bin + Me.bin ) and UART fix ( https://review.coreboot.org/c/coreboot/+/36319) board can boot till UEFI payload shell.
not yet working : cannot boot to Linux and MRC is not working.
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35923 )
Change subject: mb/intel/saddlebrook: migrate to FSP 2.0 ......................................................................
Patch Set 9:
Patch Set 9:
Patch Set 9:
Patch Set 9:
Patch Set 7:
@PraveenX would you mind testing this?
what is the expectation for test ? Boot test ?
Well, in the best case the device boots and works just like before :-)
Able to build with this patch,initially not able to boot & cannot see serial logs. later changing to 16MB ROM SIZE(adding decriptor.bin + Me.bin ) and UART fix ( https://review.coreboot.org/c/coreboot/+/36319) board can boot till UEFI payload shell.
not yet working : cannot boot to Linux and MRC is not working.
did it work before the transition to fsp2.0?
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35923 )
Change subject: mb/intel/saddlebrook: migrate to FSP 2.0 ......................................................................
Patch Set 9:
Patch Set 9:
Patch Set 9:
Patch Set 9:
Patch Set 9:
Patch Set 7:
@PraveenX would you mind testing this?
what is the expectation for test ? Boot test ?
Well, in the best case the device boots and works just like before :-)
Able to build with this patch,initially not able to boot & cannot see serial logs. later changing to 16MB ROM SIZE(adding decriptor.bin + Me.bin ) and UART fix ( https://review.coreboot.org/c/coreboot/+/36319) board can boot till UEFI payload shell.
not yet working : cannot boot to Linux and MRC is not working.
did it work before the transition to fsp2.0?
iow. test what the current state is without this cb applied, please
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35923 )
Change subject: mb/intel/saddlebrook: migrate to FSP 2.0 ......................................................................
Patch Set 9: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/35923/7//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35923/7//COMMIT_MSG@17 PS7, Line 17: TODO: : - testing
well, shouldn't this be tested before merging? I don't have the board, so someone else needs to test […]
Done
Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/35923 )
Change subject: mb/intel/saddlebrook: migrate to FSP 2.0 ......................................................................
mb/intel/saddlebrook: migrate to FSP 2.0
This patch is part of the patch series to drop support for FSP 1.1 in soc/intel/skylake.
The following modifications have been done to migrate the board(s) from FSP 1.1 to FSP 2.0:
- remove deprecated devicetree VR_RING domain (only 4 domains in FSP 2.0)
TODO: - testing
Change-Id: I7481f3413de6780df01d9b769bd4f16d439f087c Signed-off-by: Michael Niewöhner foss@mniewoehner.de Signed-off-by: Matt DeVillier matt.devillier@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/35923 Reviewed-by: Michael Niewöhner Reviewed-by: Wim Vervoorn Reviewed-by: Aaron Durbin adurbin@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/intel/saddlebrook/Kconfig M src/mainboard/intel/saddlebrook/devicetree.cb M src/mainboard/intel/saddlebrook/ramstage.c M src/mainboard/intel/saddlebrook/romstage.c 4 files changed, 69 insertions(+), 84 deletions(-)
Approvals: build bot (Jenkins): Verified Aaron Durbin: Looks good to me, approved Matt DeVillier: Looks good to me, approved Wim Vervoorn: Looks good to me, but someone else must approve Michael Niewöhner: Looks good to me, but someone else must approve
diff --git a/src/mainboard/intel/saddlebrook/Kconfig b/src/mainboard/intel/saddlebrook/Kconfig index 934c15a..3fb694a 100644 --- a/src/mainboard/intel/saddlebrook/Kconfig +++ b/src/mainboard/intel/saddlebrook/Kconfig @@ -32,6 +32,7 @@ select HAVE_CMOS_DEFAULT select MAINBOARD_USES_IFD_GBE_REGION select USE_INTEL_FSP_MP_INIT + select MAINBOARD_USES_FSP2_0
config IRQ_SLOT_COUNT int diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index 3322bf8..385a4be 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -61,82 +61,70 @@
register "serirq_mode" = "SERIRQ_CONTINUOUS"
- # VR Settings Configuration for 5 Domains - #+----------------+-------+-------+-------------+-------------+-------+ - #| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT | - #+----------------+-------+-------+-------------+-------------+-------+ - #| Psi1Threshold | 20A | 20A | 20A | 20A | 20A | - #| Psi2Threshold | 4A | 5A | 5A | 5A | 5A | - #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A | - #| Psi3Enable | 1 | 1 | 1 | 1 | 1 | - #| Psi4Enable | 1 | 1 | 1 | 1 | 1 | - #| ImonSlope | 0 | 0 | 0 | 0 | 0 | - #| ImonOffset | 0 | 0 | 0 | 0 | 0 | - #| IccMax | 7A | 34A | 34A | 35A | 35A | - #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V | - #+----------------+-------+-------+-------------+-------------+-------+ + # VR Settings Configuration for 4 Domains + #+----------------+-----------+-----------+-------------+----------+ + #| Domain/Setting | SA | IA | GT Unsliced | GT | + #+----------------+-----------+-----------+-------------+----------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 4A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| IccMax | 7A | 34A | 35A | 35A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #+----------------+-----------+-----------+-------------+----------+ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ - .vr_config_enable = 1, \ - .psi1threshold = 0x50, \ - .psi2threshold = 0x10, \ - .psi3threshold = 0x4, \ - .psi3enable = 1, \ - .psi4enable = 1, \ - .imon_slope = 0x0, \ - .imon_offset = 0x0, \ - .icc_max = 0x1C, \ - .voltage_limit = 0x5F0 \ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(4), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(7), + .voltage_limit = 1520, }"
register "domain_vr_config[VR_IA_CORE]" = "{ - .vr_config_enable = 1, \ - .psi1threshold = 0x50, \ - .psi2threshold = 0x14, \ - .psi3threshold = 0x4, \ - .psi3enable = 1, \ - .psi4enable = 1, \ - .imon_slope = 0x0, \ - .imon_offset = 0x0, \ - .icc_max = 0x88, \ - .voltage_limit = 0x5F0 \ - }" - register "domain_vr_config[VR_RING]" = "{ - .vr_config_enable = 1, \ - .psi1threshold = 0x50, \ - .psi2threshold = 0x14, \ - .psi3threshold = 0x4, \ - .psi3enable = 1, \ - .psi4enable = 1, \ - .imon_slope = 0x0, \ - .imon_offset = 0x0, \ - .icc_max = 0x88, \ - .voltage_limit = 0x5F0, \ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(34), + .voltage_limit = 1520, }"
register "domain_vr_config[VR_GT_UNSLICED]" = "{ - .vr_config_enable = 1, \ - .psi1threshold = 0x50, \ - .psi2threshold = 0x14, \ - .psi3threshold = 0x4, \ - .psi3enable = 1, \ - .psi4enable = 1, \ - .imon_slope = 0x0, \ - .imon_offset = 0x0, \ - .icc_max = 0x8C ,\ - .voltage_limit = 0x5F0 \ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(35), + .voltage_limit = 1520, }"
register "domain_vr_config[VR_GT_SLICED]" = "{ - .vr_config_enable = 1, \ - .psi1threshold = 0x50, \ - .psi2threshold = 0x14, \ - .psi3threshold = 0x4, \ - .psi3enable = 1, \ - .psi4enable = 1, \ - .imon_slope = 0x0, \ - .imon_offset = 0x0, \ - .icc_max = 0x8C, \ - .voltage_limit = 0x5F0 \ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(35), + .voltage_limit = 1520, }"
# Enable x1 slot diff --git a/src/mainboard/intel/saddlebrook/ramstage.c b/src/mainboard/intel/saddlebrook/ramstage.c index 42477e6..ed37681 100644 --- a/src/mainboard/intel/saddlebrook/ramstage.c +++ b/src/mainboard/intel/saddlebrook/ramstage.c @@ -16,7 +16,7 @@ #include <soc/ramstage.h> #include "gpio.h"
-void mainboard_silicon_init_params(SILICON_INIT_UPD *params) +void mainboard_silicon_init_params(FSP_SIL_UPD *params) { /* Configure pads prior to SiliconInit() in case there's any * dependencies during hardware initialization. */ diff --git a/src/mainboard/intel/saddlebrook/romstage.c b/src/mainboard/intel/saddlebrook/romstage.c index 0ed6730..8e280de 100644 --- a/src/mainboard/intel/saddlebrook/romstage.c +++ b/src/mainboard/intel/saddlebrook/romstage.c @@ -24,10 +24,10 @@ #include <spd_bin.h>
-void mainboard_memory_init_params( - struct romstage_params *params, - MEMORY_INIT_UPD *memory_params) +void mainboard_memory_init_params(FSPM_UPD *mupd) { + FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; + struct spd_block blk = { .addr_map = { 0x50, 0x52, }, }; @@ -36,26 +36,22 @@ dump_spd_info(&blk); printk(BIOS_SPEW, "spd block length: 0x%08x\n", blk.len);
- memory_params->MemorySpdPtr00 = (UINT32) blk.spd_array[0]; - memory_params->MemorySpdPtr10 = (UINT32) blk.spd_array[1]; - printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_0_0\n", - memory_params->MemorySpdPtr00); - printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_1_0\n", - memory_params->MemorySpdPtr10); + mem_cfg->MemorySpdPtr00 = (UINT32) blk.spd_array[0]; + mem_cfg->MemorySpdPtr10 = (UINT32) blk.spd_array[1]; + printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_0_0\n", mem_cfg->MemorySpdPtr00); + printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_1_0\n", mem_cfg->MemorySpdPtr10);
/* * Configure the DQ/DQS settings if required. In general the settings * should be set in the FSP flash image and should not need to be * changed. */ - mainboard_fill_dq_map_data(&memory_params->DqByteMapCh0, - &memory_params->DqByteMapCh1); - mainboard_fill_dqs_map_data(&memory_params->DqsMapCpu2DramCh0, - &memory_params->DqsMapCpu2DramCh1); - mainboard_fill_rcomp_res_data(&memory_params->RcompResistor); - mainboard_fill_rcomp_strength_data(&memory_params->RcompTarget); + mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0, &mem_cfg->DqByteMapCh1); + mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0, &mem_cfg->DqsMapCpu2DramCh1); + mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); + mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget);
/* update spd length*/ - memory_params->MemorySpdDataLen = blk.len; - memory_params->DqPinsInterleaved = TRUE; + mem_cfg->MemorySpdDataLen = blk.len; + mem_cfg->DqPinsInterleaved = TRUE; }
-
Aaron Durbin (Code Review) -
Matt DeVillier (Code Review)
-
Michael Niewöhner (Code Review)
-
Nico Huber (Code Review)
-
Patrick Georgi (Code Review)
-
PraveenX Hodagatta Pranesh (Code Review)
-
Wim Vervoorn (Code Review)